[PATCH] D83872: [AMDGPU] Update VMEM scalar write hazard mitigation sequence

[Jay Foad via Phabricator via llvm-commits]

foad accepted this revision.
foad added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp:935-938
                   (MI->getOpcode() == AMDGPU::S_WAITCNT &&
-                   !MI->getOperand(0).getImm()));
+                   !MI->getOperand(0).getImm()) ||
+                  (MI->getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
+                   MI->getOperand(0).getImm() == 0xffe3));
----------------
I wonder if there is a way to generalise this to spot any waitcnt that would mitigate the hazard, rather than just these two specific cases. But I guess this is fine in practice.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83872/new/

https://reviews.llvm.org/D83872