[PATCH] D83825: AMDGPU: Rename add/sub with carry out instructions

Tue Jul 14 15:36:43 PDT 2020

arsenm created this revision.
arsenm added reviewers: dp, vpykhtin, rampitec, foad.
Herald added subscribers: kerbowa, arphaman, kbarton, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, nemanjai, kzhuravl, qcolombet.
Herald added a project: LLVM.

The hardware has created a real mess in the naming for add/sub, which
have been renamed basically every generation. Switch the carry out
pseudos to have the gfx9/gfx10 names. We were using the original SI/CI
v_add_i32/v_sub_i32 names. Later targets reintroduced these names as
carryless instructions with a saturating clamp bit, which we do not
define. Do this rename so we can unambiguously add these missing
instructions.

The carry-in versions should also be renamed, but at least those had a
consistent _u32 name to begin with. The 16-bit instructions were also
renamed, but aren't ambiguous.

This does regress assembler error message quality in some cases. In
mismatched wave32/wave64 situations, this will switch from
"unsupported instruction" to "invalid operand", with the error
pointing at the wrong position. I couldn't quite follow how the
assembler selects these, but the previous behavior seemed accidental
to me. It looked like there was a partial attempt to handle this which
was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it
isn't used for anything).

https://reviews.llvm.org/D83825

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/carryout-selection.ll
  llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
  llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
  llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
  llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
  llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
  llvm/test/CodeGen/AMDGPU/dpp_combine.mir
  llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
  llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
  llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
  llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
  llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
  llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
  llvm/test/CodeGen/AMDGPU/global-load-store-atomics.mir
  llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
  llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
  llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
  llvm/test/CodeGen/AMDGPU/merge-load-store.mir
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
  llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
  llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
  llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
  llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
  llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
  llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
  llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
  llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
  llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
  llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
  llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
  llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
  llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
  llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
  llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
  llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
  llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
  llvm/test/CodeGen/AMDGPU/wqm.mir
  llvm/test/MC/AMDGPU/wave32.s

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