[PATCH] D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions

[Paolo Savini via Phabricator via llvm-commits]

PaoloS marked 2 inline comments as done.
PaoloS added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32Zbt.ll:151
+
+define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
+; RV32I-LABEL: fshl_i64:
----------------
lewis-revill wrote:
> Nitpick: See comment on first patch regarding these extra tests.
There is actually a small improvement of the code size made by some cmov instructions. But its quite small, so I'll comment it anyway.


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https://reviews.llvm.org/D79875