[PATCH] D83641: [AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec accepted this revision.
rampitec added a comment.
This revision is now accepted and ready to land.

LGTM with a nit.



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Comment at: llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp:137
+  if (A->getOpcode() == AndN2)
+    MaskValue = MaskValue == 0 ? -1 : 0;
+
----------------
It is MaskValue = ~MaskValue; right? I think it is just more clear with negation.


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Comment at: llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp:129
+  } else if (Op2.isImm()) {
+    MaskValue = Op2.getImm();
   }
----------------
critson wrote:
> rampitec wrote:
> > Technically here MaskValue can be anything, not just -1 or 0.
> Line 102 ensures MaskValue is 0 or -1.
> I can add an assertion here as well.
OK, see it. Thanks.


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Comment at: llvm/test/CodeGen/AMDGPU/infinite-loop.ll:161
 ; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; SI-NEXT:    s_and_b64 vcc, exec, 0
+; SI-NEXT:    s_branch BB3_2
----------------
critson wrote:
> rampitec wrote:
> > Looks like s_mov_b64 vcc, 0?
> Yes, hence how this becomes an unconditional branch.
> Are you suggesting that we add a peephole to clean up "s_and_b* vcc, exec, 0" -> "s_mov_b* vcc, 0" in this case ?
Yes, but not in this change.


Repository:
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  https://reviews.llvm.org/D83641/new/

https://reviews.llvm.org/D83641