[PATCH] D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:675
+// There's no encoding for roli as it can be implemented with rori by negating
+// the immediate.
+let Predicates = [HasStdExtZbbOrZbp] in
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A little confused by this comment here, do you mean there is no pattern matching rather than there is no encoding.


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Comment at: llvm/test/CodeGen/RISCV/rv32Zbbp.ll:432
+
+define i64 @ror_i64(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: ror_i64:
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Nitpick: See comment on first patch regarding these extra tests.


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  https://reviews.llvm.org/D79873/new/

https://reviews.llvm.org/D79873