[llvm] 0cbdd2a - [RISCV] Fix isStoreToStackSlot

[Roger Ferrer Ibanez via llvm-commits]

Author: Roger Ferrer Ibanez
Date: 2020-07-14T12:36:42Z
New Revision: 0cbdd2a82ad84dc9c70341a8900506cc5676edfe

URL: https://github.com/llvm/llvm-project/commit/0cbdd2a82ad84dc9c70341a8900506cc5676edfe
DIFF: https://github.com/llvm/llvm-project/commit/0cbdd2a82ad84dc9c70341a8900506cc5676edfe.diff

LOG: [RISCV] Fix isStoreToStackSlot

Because of the layout of stores (that don't have a destination operand)
this check is exactly the same as the one in
RISCVInstrInfo::isLoadFromStackSlot.

Differential Revision: https://reviews.llvm.org/D81805

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/test/CodeGen/RISCV/stack-store-check.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index f64e4397dcd3..dc212d9cde2e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -76,10 +76,10 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
     break;
   }
 
-  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
-      MI.getOperand(1).getImm() == 0) {
-    FrameIndex = MI.getOperand(0).getIndex();
-    return MI.getOperand(2).getReg();
+  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
+      MI.getOperand(2).getImm() == 0) {
+    FrameIndex = MI.getOperand(1).getIndex();
+    return MI.getOperand(0).getReg();
   }
 
   return 0;

diff  --git a/llvm/test/CodeGen/RISCV/stack-store-check.ll b/llvm/test/CodeGen/RISCV/stack-store-check.ll
index 4183dbee2d4a..c8f733bd6ce9 100644
--- a/llvm/test/CodeGen/RISCV/stack-store-check.ll
+++ b/llvm/test/CodeGen/RISCV/stack-store-check.ll
@@ -98,7 +98,6 @@ define void @main() local_unnamed_addr nounwind {
 ; CHECK-NEXT:    sw a0, 308(sp)
 ; CHECK-NEXT:    sw a3, 304(sp)
 ; CHECK-NEXT:    sw a2, 300(sp)
-; CHECK-NEXT:    lw a0, 52(sp)
 ; CHECK-NEXT:    sw a1, 296(sp)
 ; CHECK-NEXT:    sw s11, 324(sp)
 ; CHECK-NEXT:    sw s9, 320(sp)