[PATCH] D81648: MIR Statepoint refactoring. Part 4: ISEL changes.

[Denis Antrushin via Phabricator via llvm-commits]

dantrushin updated this revision to Diff 277763.
dantrushin marked 3 inline comments as done.
dantrushin added a comment.

Another attempt to submit update.

Additionally in this version:

- Added tests (used multiple checks per function to better demonstrate how it works in practice - after ISel, after RA and resulting asm).

- Changed boolean flag to counter to simplify possible landing ahead of D81646 <https://reviews.llvm.org/D81646>.

- Use single map `LowerAsVreg` instead of pair of set `LowerAsVReg` and map `Ptr2ResNo`.

NOTES:

- This can be landed only **after** D81645 <https://reviews.llvm.org/D81645> (Part 1: Basic MI level changes).
- If landed before D81646 <https://reviews.llvm.org/D81646> (Part 2: Operand Folding), vreg limit cannot be raised too high or regalloc will run out of registers.
- If landed after D81647 <https://reviews.llvm.org/D81647> (Part 3; Spill GC Ptr regs), last run line in test must be updated to allow passing pointers in CSRs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81648/new/

https://reviews.llvm.org/D81648

Files:
  llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/StatepointLowering.h
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/test/CodeGen/X86/statepoint-vreg.ll

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