[PATCH] D81805: [RISCV] Fix isStoreToStackSlot

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 updated this revision to Diff 277689.
rogfer01 added a comment.

ChangeLog:

- Update test from D83750 <https://reviews.llvm.org/D83750>


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81805/new/

https://reviews.llvm.org/D81805

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/stack-store-check.ll


Index: llvm/test/CodeGen/RISCV/stack-store-check.ll
===================================================================
--- llvm/test/CodeGen/RISCV/stack-store-check.ll
+++ llvm/test/CodeGen/RISCV/stack-store-check.ll
@@ -98,7 +98,6 @@
 ; CHECK-NEXT:    sw a0, 308(sp)
 ; CHECK-NEXT:    sw a3, 304(sp)
 ; CHECK-NEXT:    sw a2, 300(sp)
-; CHECK-NEXT:    lw a0, 52(sp)
 ; CHECK-NEXT:    sw a1, 296(sp)
 ; CHECK-NEXT:    sw s11, 324(sp)
 ; CHECK-NEXT:    sw s9, 320(sp)
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -76,10 +76,10 @@
     break;
   }
 
-  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
-      MI.getOperand(1).getImm() == 0) {
-    FrameIndex = MI.getOperand(0).getIndex();
-    return MI.getOperand(2).getReg();
+  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
+      MI.getOperand(2).getImm() == 0) {
+    FrameIndex = MI.getOperand(1).getIndex();
+    return MI.getOperand(0).getReg();
   }
 
   return 0;


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