[llvm] 74c1420 - [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
Carl Ritson via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 20:54:24 PDT 2020
Author: Carl Ritson
Date: 2020-07-14T12:53:43+09:00
New Revision: 74c14202d90b46dda64a2542602855727b7d7f60
URL: https://github.com/llvm/llvm-project/commit/74c14202d90b46dda64a2542602855727b7d7f60
DIFF: https://github.com/llvm/llvm-project/commit/74c14202d90b46dda64a2542602855727b7d7f60.diff
LOG: [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
Preserve SCC dead flags in SIOptimizeExecMaskingPreRA.
This helps with removing redundant s_andn2 instructions later.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D83637
Added:
Modified:
llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index 7eb1ec941dbd..8af00fcf62a8 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -168,6 +168,11 @@ static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
And->getOperand(0).getReg())
.addReg(ExecReg)
.addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
+ MachineOperand &AndSCC = And->getOperand(3);
+ assert(AndSCC.getReg() == AMDGPU::SCC);
+ MachineOperand &Andn2SCC = Andn2->getOperand(3);
+ assert(Andn2SCC.getReg() == AMDGPU::SCC);
+ Andn2SCC.setIsDead(AndSCC.isDead());
And->eraseFromParent();
LIS->InsertMachineInstrInMaps(*Andn2);
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
index 4a69057b1f10..e5a7421dbd5d 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
@@ -104,7 +104,7 @@ body: |
; GCN-LABEL: name: cndmask_cmp_cbranch_fold_undef
; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000)
- ; GCN: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def $scc
+ ; GCN: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def dead $scc
; GCN: S_CBRANCH_VCCZ %bb.1, implicit $vcc
; GCN: bb.1:
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
index 91bb625ddad7..7da54744b8c4 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
@@ -2,7 +2,7 @@
# GCN: name: negated_cond_vop2
# GCN: %0:sgpr_32 = IMPLICIT_DEF
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2
@@ -24,7 +24,7 @@ body: |
# GCN: name: negated_cond_vop3
# GCN: %0:sgpr_32 = IMPLICIT_DEF
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3
@@ -116,7 +116,7 @@ body: |
# GCN: name: negated_cond_vop3_imp_vcc
# GCN: $vcc_lo = IMPLICIT_DEF
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3_imp_vcc
@@ -138,7 +138,7 @@ body: |
# GCN: name: negated_cond_vop2_imp_vcc
# GCN: $vcc_lo = IMPLICIT_DEF
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2_imp_vcc
@@ -187,7 +187,7 @@ body: |
# GCN: name: negated_cond_vop2_used_sel
# GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2_used_sel
@@ -213,7 +213,7 @@ body: |
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2_used_vcc
@@ -289,7 +289,7 @@ body: |
# GCN: name: negated_cond_vop3_sel_right_subreg1
# GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3_sel_right_subreg1
@@ -313,7 +313,7 @@ body: |
# GCN: name: negated_cond_vop3_sel_right_subreg2
# GCN: %0:sgpr_32 = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
-# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def $scc
+# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3_sel_right_subreg2
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
index c70474bf8c39..24e1ec81cb3a 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
@@ -2,7 +2,7 @@
# GCN: name: negated_cond_vop2
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2
@@ -24,7 +24,7 @@ body: |
# GCN: name: negated_cond_vop3
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3
@@ -142,7 +142,7 @@ body: |
# GCN: name: negated_cond_vop3_imp_vcc
# GCN: $vcc = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3_imp_vcc
@@ -164,7 +164,7 @@ body: |
# GCN: name: negated_cond_vop2_imp_vcc
# GCN: $vcc = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2_imp_vcc
@@ -213,7 +213,7 @@ body: |
# GCN: name: negated_cond_vop2_used_sel
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2_used_sel
@@ -239,7 +239,7 @@ body: |
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop2_used_vcc
@@ -315,7 +315,7 @@ body: |
# GCN: name: negated_cond_vop3_sel_right_subreg1
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3_sel_right_subreg1
@@ -339,7 +339,7 @@ body: |
# GCN: name: negated_cond_vop3_sel_right_subreg2
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_vop3_sel_right_subreg2
@@ -388,7 +388,7 @@ body: |
# GCN: name: negated_cond_vop2_dominated_blocks
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
-# GCN: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
+# GCN: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
---
name: negated_cond_vop2_dominated_blocks
@@ -466,7 +466,7 @@ body: |
# GCN: name: negated_cond_subreg
# GCN: %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
-# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def $scc
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def dead $scc
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
---
name: negated_cond_subreg
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