[llvm] 62f5ba6 - [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang
Amy Kwan via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 20:48:03 PDT 2020
Author: Amy Kwan
Date: 2020-07-13T22:47:47-05:00
New Revision: 62f5ba624bfba5ccf4446737ad2bfb1fc013b376
URL: https://github.com/llvm/llvm-project/commit/62f5ba624bfba5ccf4446737ad2bfb1fc013b376
DIFF: https://github.com/llvm/llvm-project/commit/62f5ba624bfba5ccf4446737ad2bfb1fc013b376.diff
LOG: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang
This patch implements builtins for the Test LSB by Byte instruction introduced
in Power10.
Differential Revision: https://reviews.llvm.org/D82431
Added:
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index d0df5fcd1552..6b291e6b0806 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -467,6 +467,8 @@ BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
+BUILTIN(__builtin_vsx_xvtlsbb, "iV16Ucb", "")
+
// P10 Vector Permute Extended built-in.
BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 9a4009216930..ac5f43836316 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -17146,6 +17146,20 @@ vec_splati_ins(vector float __a, const unsigned int __b, const float __c) {
#endif
return __a;
}
+
+/* vec_test_lsbb_all_ones */
+
+static __inline__ int __ATTRS_o_ai
+vec_test_lsbb_all_ones(vector unsigned char __a) {
+ return __builtin_vsx_xvtlsbb(__a, 1);
+}
+
+/* vec_test_lsbb_all_zeros */
+
+static __inline__ int __ATTRS_o_ai
+vec_test_lsbb_all_zeros(vector unsigned char __a) {
+ return __builtin_vsx_xvtlsbb(__a, 0);
+}
#endif /* __VSX__ */
#endif /* __POWER10_VECTOR__ */
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 22b4e7a6f3ec..c51c24f25986 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -581,3 +581,15 @@ vector float test_vec_vec_splati_ins_f(void) {
// CHECK: ret <4 x float>
return vec_splati_ins(vfa, 0, 1.0f);
}
+
+int test_vec_test_lsbb_all_ones(void) {
+ // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 true
+ // CHECK-NEXT: ret i32
+ return vec_test_lsbb_all_ones(vuca);
+}
+
+int test_vec_test_lsbb_all_zeros(void) {
+ // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 false
+ // CHECK-NEXT: ret i32
+ return vec_test_lsbb_all_zeros(vuca);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 12f4a3ce8e28..614a29049686 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1067,6 +1067,9 @@ def int_ppc_vsx_xxinsertw :
PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
[llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
[IntrNoMem]>;
+def int_ppc_vsx_xvtlsbb :
+ PowerPC_VSX_Intrinsic<"xvtlsbb", [llvm_i32_ty],
+ [llvm_v16i8_ty, llvm_i1_ty], [IntrNoMem]>;
def int_ppc_vsx_xxeval :
PowerPC_VSX_Intrinsic<"xxeval", [llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 2d12a72e29ae..2bab73418e10 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -396,6 +396,25 @@ class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
let Inst{63} = XT{5};
}
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
+ dag IOL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> BF;
+ bits<6> XB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = BF;
+ let Inst{9-10} = 0;
+ let Inst{11-15} = xo2;
+ let Inst{16-20} = XB{4-0};
+ let Inst{21-29} = xo;
+ let Inst{30} = XB{5};
+ let Inst{31} = 0;
+}
+
multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -943,6 +962,9 @@ let Predicates = [IsISA3_1] in {
[(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+ def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
+ "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
+
// The XFormMemOp flag for the following 8 instructions is set on
// the instruction format.
let mayLoad = 1, mayStore = 0 in {
@@ -960,8 +982,6 @@ let Predicates = [IsISA3_1] in {
}
}
-
-
//---------------------------- Anonymous Patterns ----------------------------//
let Predicates = [IsISA3_1] in {
def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
@@ -972,6 +992,10 @@ let Predicates = [IsISA3_1] in {
(v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
(v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
+ def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)),
+ (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
+ def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
+ (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
}
let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
new file mode 100644
index 000000000000..d4e71d18c6eb
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s
+
+; These test cases aims to test the builtins for the Power10 VSX vector
+; instructions introduced in ISA 3.1.
+
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+
+define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvtlsbb cr0, v2
+; CHECK-NEXT: mfocrf r3, 128
+; CHECK-NEXT: srwi r3, r3, 31
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1)
+ ret i32 %0
+}
+
+define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
+; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvtlsbb cr0, v2
+; CHECK-NEXT: mfocrf r3, 128
+; CHECK-NEXT: rlwinm r3, r3, 3, 31, 31
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0)
+ ret i32 %0
+}
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