[PATCH] D83641: [AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns

[Carl Ritson via Phabricator via llvm-commits]

critson marked 3 inline comments as done.
critson added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp:129
+  } else if (Op2.isImm()) {
+    MaskValue = Op2.getImm();
   }
----------------
rampitec wrote:
> Technically here MaskValue can be anything, not just -1 or 0.
Line 102 ensures MaskValue is 0 or -1.
I can add an assertion here as well.


================
Comment at: llvm/test/CodeGen/AMDGPU/infinite-loop.ll:161
 ; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; SI-NEXT:    s_and_b64 vcc, exec, 0
+; SI-NEXT:    s_branch BB3_2
----------------
rampitec wrote:
> Looks like s_mov_b64 vcc, 0?
Yes, hence how this becomes an unconditional branch.
Are you suggesting that we add a peephole to clean up "s_and_b* vcc, exec, 0" -> "s_mov_b* vcc, 0" in this case ?


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Comment at: llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll:14
 ; SI:       ; %bb.0: ; %entry
-; SI-NEXT:	s_load_dwordx4 s[4:7], s[0:1], 0xb
-; SI-NEXT:	s_load_dword s2, s[0:1], 0xf
-; SI-NEXT:	s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT:	s_waitcnt lgkmcnt(0)
-; SI-NEXT:	s_cmp_lg_u32 s4, 0
-; SI-NEXT:	s_cbranch_scc0 BB0_2
-; SI-NEXT:; %bb.1:                                ; %else
-; SI-NEXT:	s_add_i32 s2, s7, s2
-; SI-NEXT:	s_mov_b64 s[8:9], 0
-; SI-NEXT:	s_andn2_b64 vcc, exec, s[8:9]
-; SI-NEXT:	s_cbranch_vccz BB0_3
-; SI-NEXT:	s_branch BB0_4
-; SI-NEXT:BB0_2:
-; SI-NEXT:	s_mov_b64 s[8:9], -1
-; SI-NEXT:                                        ; implicit-def: $sgpr2
-; SI-NEXT:	s_andn2_b64 vcc, exec, s[8:9]
-; SI-NEXT:	s_cbranch_vccnz BB0_4
-; SI-NEXT:BB0_3:                                  ; %if
-; SI-NEXT:	s_sub_i32 s2, s5, s6
-; SI-NEXT:BB0_4:                                  ; %endif
-; SI-NEXT:	s_add_i32 s4, s2, s4
-; SI-NEXT:	s_mov_b32 s3, 0xf000
-; SI-NEXT:	s_mov_b32 s2, -1
-; SI-NEXT:	v_mov_b32_e32 v0, s4
-; SI-NEXT:	buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT:	s_endpgm
+; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
+; SI-NEXT:    s_load_dword s2, s[0:1], 0xf
----------------
rampitec wrote:
> Do you mind to pre-commit white space changes?
Will do.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D83641/new/

https://reviews.llvm.org/D83641