[llvm] eafe7c1 - [PowerPC] Fix combineVectorShuffle regression after D77448
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 16:57:36 PDT 2020
Author: Fangrui Song
Date: 2020-07-13T16:57:27-07:00
New Revision: eafe7c14ea38946e8c1fb64d548effaee7614718
URL: https://github.com/llvm/llvm-project/commit/eafe7c14ea38946e8c1fb64d548effaee7614718
DIFF: https://github.com/llvm/llvm-project/commit/eafe7c14ea38946e8c1fb64d548effaee7614718.diff
LOG: [PowerPC] Fix combineVectorShuffle regression after D77448
Commit 1fed131660b2 assumed that NewShuffle (shuffle vector
canonicalization result) will always be ShuffleVectorSDNode, which may
be false (it may be a BITCAST node):
```
...
t12: v4i32 = scalar_to_vector t2
t15: v16i8 = bitcast t12 # LHS
t17: v16i8 = vector_shuffle<u,u,u,u,u,u,u,u,0,1,2,3,u,u,u,u> t15, undef:v16i8 # SVN
```
Reviewed By: #powerpc, nemanjai
Differential Revision: https://reviews.llvm.org/D83617
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 575ad68fecd9..ddfbd04e1ebc 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -9896,6 +9896,8 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
// to vector legalization will not be sent to the target combine. Try to
// combine it here.
if (SDValue NewShuffle = combineVectorShuffle(SVOp, DAG)) {
+ if (!isa<ShuffleVectorSDNode>(NewShuffle))
+ return NewShuffle;
Op = NewShuffle;
SVOp = cast<ShuffleVectorSDNode>(Op);
V1 = Op.getOperand(0);
diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
index ada7c73cd9ed..cc349ec228f4 100644
--- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
+++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
@@ -343,30 +343,57 @@ test_entry:
unreachable
}
+define dso_local <16 x i8> @no_crash_bitcast(i32 %a) {
+; CHECK-P8-LABEL: no_crash_bitcast:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mtvsrwz v2, r3
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P9-LABEL: no_crash_bitcast:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: mtvsrws v2, r3
+; CHECK-P9-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: no_crash_bitcast:
+; CHECK-NOVSX: # %bb.0: # %entry
+; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI14_0 at toc@ha
+; CHECK-NOVSX-NEXT: stw r3, -16(r1)
+; CHECK-NOVSX-NEXT: addi r3, r1, -16
+; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI14_0 at toc@l
+; CHECK-NOVSX-NEXT: lvx v3, 0, r3
+; CHECK-NOVSX-NEXT: lvx v2, 0, r4
+; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2
+; CHECK-NOVSX-NEXT: blr
+entry:
+ %cast = bitcast i32 %a to <4 x i8>
+ %ret = shufflevector <4 x i8> %cast, <4 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+ ret <16 x i8> %ret
+}
+
define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: replace_undefs_in_splat:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: addis r3, r2, .LCPI14_0 at toc@ha
-; CHECK-P8-NEXT: addi r3, r3, .LCPI14_0 at toc@l
+; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0 at toc@ha
+; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0 at toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vmrgow v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: replace_undefs_in_splat:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: addis r3, r2, .LCPI14_0 at toc@ha
-; CHECK-P9-NEXT: addi r3, r3, .LCPI14_0 at toc@l
+; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0 at toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0 at toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: vmrgow v2, v3, v2
; CHECK-P9-NEXT: blr
;
; CHECK-NOVSX-LABEL: replace_undefs_in_splat:
; CHECK-NOVSX: # %bb.0: # %entry
-; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI14_0 at toc@ha
-; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI14_1 at toc@ha
-; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI14_0 at toc@l
+; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI15_0 at toc@ha
+; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI15_1 at toc@ha
+; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI15_0 at toc@l
; CHECK-NOVSX-NEXT: lvx v3, 0, r3
-; CHECK-NOVSX-NEXT: addi r3, r4, .LCPI14_1 at toc@l
+; CHECK-NOVSX-NEXT: addi r3, r4, .LCPI15_1 at toc@l
; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3
; CHECK-NOVSX-NEXT: blr
@@ -378,10 +405,10 @@ entry:
define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture readonly %ptr, i32 signext %offset) local_unnamed_addr #0 {
; CHECK-P8-LABEL: no_RAUW_in_combine_during_legalize:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: addis r5, r2, .LCPI15_0 at toc@ha
+; CHECK-P8-NEXT: addis r5, r2, .LCPI16_0 at toc@ha
; CHECK-P8-NEXT: sldi r4, r4, 2
; CHECK-P8-NEXT: xxlxor v4, v4, v4
-; CHECK-P8-NEXT: addi r5, r5, .LCPI15_0 at toc@l
+; CHECK-P8-NEXT: addi r5, r5, .LCPI16_0 at toc@l
; CHECK-P8-NEXT: lxsiwzx v2, r3, r4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: vperm v2, v4, v2, v3
@@ -391,8 +418,8 @@ define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture re
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: sldi r4, r4, 2
; CHECK-P9-NEXT: lxsiwzx v2, r3, r4
-; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0 at toc@ha
-; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0 at toc@l
+; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0 at toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0 at toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3
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