[PATCH] D83617: [PowerPC] Fix combineVectorShuffle regression after D77448

Nemanja Ivanovic via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 13 16:31:53 PDT 2020


nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for fixing this.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9895
+  if (SDValue NewShuffle = combineVectorShuffle(SVOp, DAG))
+    if (isa<ShuffleVectorSDNode>(NewShuffle)) {
+      Op = NewShuffle;
----------------
If the result is not a shuffle, I don't think we need to continue custom lowering it here. Perhaps this should just be:
```
if (!isa<ShuffleVectorSDNode>(NewShuffle))
  return NewShuffle;
```



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83617/new/

https://reviews.llvm.org/D83617





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