[PATCH] D83724: [PowerPC][Power10] Add Vector Extract/Expand/Count with Mask, Move to VSR Mask Instruction Definitions and MC Tests

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: PowerPC, power-llvm-team.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, hiraditya, nemanjai.

This patch adds the instruction definitions and assembly/disassembly tests for the following set of instructions:

- Vector Extract [byte | half | word |  doubleword | quad] with mask
- Vector Expand [byte | half | word |  doubleword | quad] with mask
- Move to VSR [byte | byte immediate | half | word | doubleword | quad] with mask
- Vector Count Mask Bits [byte | half | word | doubleword]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83724

Files:
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

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