[PATCH] D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 12:08:44 PDT 2020
arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.
LGTM with nits for future vector handling
================
Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:584
+ unsigned NumSextBits =
+ MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() -
+ MI.getOperand(2).getImm();
----------------
getScalarSizeInBits
================
Comment at: llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp:448-449
+ LLT Ty = MRI.getType(Dst);
+ if (Ty.isVector())
+ break;
+ if (MI.hasOneMemOperand())
----------------
Should add TODO to handle vectors
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D81993/new/
https://reviews.llvm.org/D81993
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