[PATCH] D82988: [RISCV] Avoid Splitting MBB in RISCVExpandPseudo

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hi @lenary,

I'm sorry to report that this approach is still problematic. In some of the testcases of the LLVM test-suite the pass when built with  `-fPIC -O3`, pass `Branch Probability Basic Block Placement` decides to copy the `AUIPC` / `LD` pair but the copy carries around the same symbol. This fails with:

  fatal error: error in backend: invalid symbol redefinition

I've seen other testcases in which we trigger

  fatal error: error in backend: could not find corresponding %pcrel_hi



  bb.5.for.end55:
  ; predecessors: %bb.4
  
    renamable $x10 = AUIPC target-flags(riscv-got-hi) @perSCC, pre-instr-symbol <mcsymbol .Ltmp1>
    renamable $x10 = LD killed renamable $x10, target-flags(riscv-pcrel-lo) <mcsymbol .Ltmp1>
    renamable $x12 = LD killed renamable $x10, 0 :: (dereferenceable load 8 from @perSCC)
    PseudoCALL target-flags(riscv-plt) @SCCofVCG, <regmask $x1 $x3 $x4 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $f8_d $f9_d $f18_d $f19_d $f20_d $f21_d $f22_d $f23_d $f24_d $f25_d $f26_d $f27_d $f8_f $f9_f $f18_f $f19_f $f20_f $f21_f and 6 more...>, implicit-def dead $x1, implicit undef $x10, implicit undef $x11, implicit $x12, implicit-def $x2
  
  bb.6.if.then47:
  ; predecessors: %bb.3
    liveins: $x11
    SD $x0, killed renamable $x11, 0 :: (store 8 into %ir.4)
    renamable $x10 = AUIPC target-flags(riscv-got-hi) @perSCC, pre-instr-symbol <mcsymbol .Ltmp1>
    renamable $x10 = LD killed renamable $x10, target-flags(riscv-pcrel-lo) <mcsymbol .Ltmp1>
    renamable $x12 = LD killed renamable $x10, 0 :: (dereferenceable load 8 from @perSCC)
    PseudoCALL target-flags(riscv-plt) @SCCofVCG, <regmask $x1 $x3 $x4 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $f8_d $f9_d $f18_d $f19_d $f20_d $f21_d $f22_d $f23_d $f24_d $f25_d $f26_d $f27_d $f8_f $f9_f $f18_f $f19_f $f20_f $f21_f and 6 more...>, implicit-def dead $x1, implicit undef $x10, implicit undef $x11, implicit $x12, implicit-def $x2

I don't have many ideas here. I understand the root cause is that we can't really copy the instruction (unless we're somehow able to create a new symbol for the copied `AUIPC` and map the reference of the copied `LD` to the new one). A specific pass that fixes these cases doesn't seem very appealing either.

Kind regards,


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D82988/new/

https://reviews.llvm.org/D82988