[PATCH] D83654: [PowerPC] Support constrained vector fp/int conversion

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, jsji, uweigand, steven.zhang, kpn, PowerPC, kbarton.
Herald added subscribers: llvm-commits, shchenz, hiraditya.
Herald added a project: LLVM.

This patch makes these operations legal, and add necessary codegen patterns.

There's still some issue similar to D77033 <https://reviews.llvm.org/D77033> for conversion from/to `v1i128`, but normal type tests synced from X86/SystemZ's `vector-constrained-fp-intrinsics.ll` are all okay.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83654

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

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