[PATCH] D83602: [DAGCombiner] Scalarize splats with just one demanded lane

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
tlively added reviewers: aheejin, dschuff, arsenm, spatel.
Herald added subscribers: llvm-commits, ecnelises, hiraditya, jgravelle-google, sbc100, wdng.
Herald added a project: LLVM.

This patch implements a combine to scalarize subtrees of the selection
DAG that produce splat values for which only a single lane is
demanded. The scalarization only happens when the target supports
scalar versions of each operation in the subtree to avoid introducing
any new transitions between vector and scalar registers and to avoid
potentially-expensive expansions of scalarized operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83602

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-nvcast.ll
  llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
  llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
  llvm/test/CodeGen/X86/avx512-calling-conv.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D83602.277186.patch
Type: text/x-patch
Size: 16306 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200711/2211e82c/attachment.bin>