[PATCH] D83572: [SVE][CodeGen] Fix implicit TypeSize->uint64_t conversion in TransformFPLoadStorePair

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:15751
   if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
       Value.hasOneUse()) {
     LoadSDNode *LD = cast<LoadSDNode>(Value);
----------------
Mixing early return and non-early-return like this is confusing.  But I guess also orthogonal.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:15754
     EVT VT = LD->getMemoryVT();
     if (!VT.isFloatingPoint() ||
         VT != ST->getMemoryVT() ||
----------------
The isFloatingPoint check here seems weird; it doesn't really make sense to handle float vectors, but not int vectors.  But I guess that's orthogonal.


Repository:
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  https://reviews.llvm.org/D83572/new/

https://reviews.llvm.org/D83572