[PATCH] D83571: [RFC][WIP] New carry-less multiplication instruction llvm.experimental.clmul

[Shawn Landden via Phabricator via llvm-commits]

shawnl created this revision.
shawnl added reviewers: lebedev.ri, jyknight, kparzysz, scanon.
Herald added subscribers: llvm-commits, jdoerfert, hiraditya.
Herald added a reviewer: jdoerfert.
Herald added a project: LLVM.

  [RFC][WIP] New carry-less multiplication instruction llvm.experimental.clmul
  
  The problem I am having in continuing on this is that SelectionDAG
  has this concept of illegal types, and most of these hardware
  instructions return v1i128 even if i128 is not legal.
  
  The way I would really like to handle this is to do the necessary
  lowering BEFORE translation. This would also mean that the lowering
  doesn't have to be written twice. Once for the interpreter, and
  again for translation.
  
  However I am wondering how my i128 CTPOP lowering worked....maybe
  I just need to step through the code.


https://reviews.llvm.org/D83571

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/AArch64/clmul.ll

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