[PATCH] D83567: [DAGCombiner] allow load/store merging if pairs can be rotated into place

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: efriedma, RKSimon, lebedev.ri, craig.topper.
Herald added subscribers: ecnelises, hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

This carves out an exception for a pair of consecutive loads that are reversed from the consecutive order of a pair of stores. All of the existing profitability/legality checks for the memops remain between the 2 altered hunks of code.

This should give us the same x86 base-case asm that gcc gets in PR41098 and PR44895:
https://bugs.llvm.org/show_bug.cgi?id=41098
https://bugs.llvm.org/show_bug.cgi?id=44895

I think we are missing a potential subsequent conversion to use "movbe" if the target supports that. That might be similar to what AArch64 would use to get "rev16".


https://reviews.llvm.org/D83567

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/merge-store-dependency.ll
  llvm/test/CodeGen/X86/stores-merging.ll

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