[PATCH] D82443: [ARM] Narrowing half-precision lowering to supported CCs

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7e169cec74b0: [NFC][test] Adding fastcc test case for promoted 16-bit integer bitcasts. (authored by Puyan Lotfi <plotfi at fb.com>).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82443/new/

https://reviews.llvm.org/D82443

Files:
  llvm/test/CodeGen/ARM/arm-half-promote.ll


Index: llvm/test/CodeGen/ARM/arm-half-promote.ll
===================================================================
--- llvm/test/CodeGen/ARM/arm-half-promote.ll
+++ llvm/test/CodeGen/ARM/arm-half-promote.ll
@@ -51,3 +51,31 @@
 ; CHECK-NEXT: bx      lr
   ret { <8 x half>, <8 x half> } zeroinitializer
 }
+
+define fastcc { <8 x half>, <8 x half> } @f3() {
+; CHECK-LABEL: _f3
+; CHECK: vpush   {d8}
+; CHECK-NEXT: vmov.f64        d8, #5.000000e-01
+; CHECK-NEXT: vmov.i32        d8, #0x0
+; CHECK-NEXT: vmov.i32        d0, #0x0
+; CHECK-NEXT: vmov.i32        d1, #0x0
+; CHECK-NEXT: vmov.i32        d2, #0x0
+; CHECK-NEXT: vmov.i32        d3, #0x0
+; CHECK-NEXT: vmov.i32        d4, #0x0
+; CHECK-NEXT: vmov.i32        d5, #0x0
+; CHECK-NEXT: vmov.i32        d6, #0x0
+; CHECK-NEXT: vmov.i32        d7, #0x0
+; CHECK-NEXT: vmov.f32        s1, s16
+; CHECK-NEXT: vmov.f32        s3, s16
+; CHECK-NEXT: vmov.f32        s5, s16
+; CHECK-NEXT: vmov.f32        s7, s16
+; CHECK-NEXT: vmov.f32        s9, s16
+; CHECK-NEXT: vmov.f32        s11, s16
+; CHECK-NEXT: vmov.f32        s13, s16
+; CHECK-NEXT: vmov.f32        s15, s16
+; CHECK-NEXT: vpop    {d8}
+; CHECK-NEXT: bx      lr
+
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}
+


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