[PATCH] D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:173
+
+bool RISCVDAGToDAGISel::SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt) {
+  MVT XLenVT = Subtarget->getXLenVT();
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Indentation within these Select functions is messed up, presumably due to a mix of tabs and spaces.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:262
+bool RISCVDAGToDAGISel::SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
+  if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+      cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) {
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I'm not sure the convention other select functions for W instructions follow but perhaps an assert for IsRV64 should be added for completeness?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:641
+def SROIPat  : ComplexPattern<XLenVT, 2, "SelectSROI", [or]>;
+def SLOIWPat  : ComplexPattern<XLenVT, 2, "SelectSLOIW", [sext_inreg]>;
+def SROIWPat  : ComplexPattern<XLenVT, 2, "SelectSROIW", [or]>;
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Can these W selects be guarded for 64 bit only?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79870/new/

https://reviews.llvm.org/D79870