[PATCH] D83395: [SVE] Code generation for fixed length vector truncates.

Wed Jul 8 14:09:04 PDT 2020

efriedma added inline comments.

================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll:213
+; VBITS_GE_512: uzp1 [[A_HALFS:z[0-9]+]].h, [[A_WORDS]].h, [[A_WORDS]].h
+; VBITS_GE_512: uzp1 z0.b, [[A_HALFS]].b, [[A_HALFS]].b
+; CHECK: ret
----------------
cameron.mcinally wrote:
> Just passing by and had to comment that this is an expensive truncate. It's around 5x slower than the equivalent on x86, with 1/2 the throughput.
> 
> Might be a good candidate for a dedicated hardware instruction on future SVE revisions... 
We could experiment with using `tbl` or `compact`, if this comes up in practice.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83395/new/

https://reviews.llvm.org/D83395