[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Lei Huang via Phabricator via llvm-commits]

lei added inline comments.


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Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79
+vector signed int test_vec_dive_si(void) {
+  // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
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why does the ck stops matching at the first param?  Shouldn't we check the remaining param type and number of param are correct as well?


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:854
+                         [(set v4i32:$vD,
+                         (int_ppc_altivec_vdivesw v4i32:$vA, v4i32:$vB))]>;
   def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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nit: indent to match up with `v4i32` on the previous line.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609