[PATCH] D83384: [GlobalISel][InlineAsm] Fix buildCopy for matching input constraints

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: paquette, arsenm.
Herald added subscribers: llvm-commits, hiraditya, rovka, wdng.
Herald added a project: LLVM.

Check that input size matches size of destination reg class.
Attempt to extend input size when needed.


https://reviews.llvm.org/D83384

Files:
  llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll


Index: llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -211,3 +211,16 @@
   %1 = tail call i32 asm "ldr $0, $1", "=r,*m"(i32* %a)
   ret i32 %1
 }
+
+define void @test_anyext_input_matching_constraint() {
+  ; CHECK-LABEL: name: test_anyext_input_matching_constraint
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 655370 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+  %1 = call i16 asm sideeffect "", "=r,0"(i16 undef)
+  unreachable
+}
Index: llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -427,7 +427,23 @@
         ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
         assert(SrcRegs.size() == 1 && "Single register is expected here");
         Register Tmp = MRI->createVirtualRegister(RC);
-        MIRBuilder.buildCopy(Tmp, SrcRegs[0]);
+        Register Src = SrcRegs[0];
+        unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI);
+        unsigned TmpSize = TRI->getRegSizeInBits(Tmp, *MRI);
+        if (TmpSize < SrcSize) {
+          LLVM_DEBUG(dbgs() << "Input can't fit in destination reg class\n");
+          return false;
+        }
+        // Attempt to anyext small scalar sources.
+        if (TmpSize > SrcSize) {
+          if (!MRI->getType(Src).isValid() || !MRI->getType(Src).isScalar()) {
+            LLVM_DEBUG(dbgs() << "Can't extend input to size of destination"
+                                 " reg class\n");
+            return false;
+          }
+          Src = MIRBuilder.buildAnyExt(LLT::scalar(TmpSize), Src).getReg(0);
+        }
+        MIRBuilder.buildCopy(Tmp, Src);
 
         // Add Flag and input register operand (Tmp) to Inst. Tie Tmp to Def.
         unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);


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