[PATCH] D83231: [CodeGen] Don't combine extract + concat vectors with non-legal types

[Ties Stuij via Phabricator via llvm-commits]

stuij created this revision.
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The following combine currently breaks in the DAGCombiner:

extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x

  -> extract_vector_elt a, x

This happens because after we have combined these nodes we have inserted nodes
that use individual instances of the vector type. In the above example
i16. However this isn't a legal type on all backends. The type legalizer has
already been run, and running it again would make a mess of the nodes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83231

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll


Index: llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll
@@ -0,0 +1,17 @@
+; RUN: llc -asm-verbose=0 -mtriple aarch64-arm-none-eabi < %s | FileCheck %s
+
+; The following code previously broke in the DAGCombiner. Specifically, trying to combine:
+; extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x
+;   -> extract_vector_elt a, x
+
+define half @test_combine_extract_concat_vectors(<4 x i16> %a) nounwind {
+entry:
+  %0 = shufflevector <4 x i16> %a, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %1 = bitcast <8 x i16> %0 to <8 x half>
+  %2 = extractelement <8 x half> %1, i32 3
+  ret half %2
+}
+
+; CHECK-LABEL: test_combine_extract_concat_vectors:
+; CHECK-NEXT: mov h0, v0.h[3]
+; CHECK-NEXT: ret
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17812,8 +17812,10 @@
       Elt = (Idx < (int)NumElts) ? Idx : Idx - (int)NumElts;
       Index = DAG.getConstant(Elt, DL, Index.getValueType());
     }
-  } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS &&
-             !BCNumEltsChanged && VecVT.getVectorElementType() == ScalarVT) {
+  } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged &&
+             VecVT.getVectorElementType() == ScalarVT &&
+             TLI.isTypeLegal(
+                 VecOp.getOperand(0).getValueType().getVectorElementType())) {
     // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 0
     //      -> extract_vector_elt a, 0
     // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 1


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