[PATCH] D83153: [DAGCombiner] Prevent regression in isMulAddWithConstProfitable

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

My patch at least generate better code x86, aarch64 and riscv.

For x86's test urem-seteq-nonzero.ll, less instructions are emitted.

For aarch64's test urem-seteq-nonzero.ll,

1. 2 cases have one more instruction emitted,
2. other 2 cases have one less instruction emitted,
3. other 9 cases have no change in instruction amount, but have madd replaced by mul.

Since madd has larger latency than mul, I think my change also makes aarch64 optimized.

There is not previous case for RISCV, but my changes also does  optimization for RISCV.
For example,

  %tmp0 = add i32 %x, 1971
  %tmp1 = mul i32 %tmp0, 19

The origin llvm generates,

  addi    a1, zero, 19
  mul     a0, a0, a1
  lui     a1, 9
  addi    a1, a1, 585
  add     a0, a0, a1

And my patch optimizes it to

  addi    a0, a0, 1971
  addi    a1, zero, 19
  mul     a0, a0, a1


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D83153