[PATCH] D82540: [TargetLowering] Improve expansion of FSHL/FSHR by non-zero amount
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 3 10:44:52 PDT 2020
arsenm added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6105
+// Check that (every element of) Z is undef or not an exact multiple of BW.
+static bool isNonZeroModBitWidth(SDValue Z, unsigned BW) {
+ return ISD::matchUnaryPredicate(
----------------
!isDivisibleByBitWidth()?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82540/new/
https://reviews.llvm.org/D82540
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