[llvm] 484a36b - Enable basepointer for AIX.

[Sean Fertile via llvm-commits]

Author: Sean Fertile
Date: 2020-07-03T11:55:49-04:00
New Revision: 484a36b97ddfa3be2daec0241ac08bddefbc8a51

URL: https://github.com/llvm/llvm-project/commit/484a36b97ddfa3be2daec0241ac08bddefbc8a51
DIFF: https://github.com/llvm/llvm-project/commit/484a36b97ddfa3be2daec0241ac08bddefbc8a51.diff

LOG: Enable basepointer for AIX.

Differential Revision: https://reviews.llvm.org/D82030

Added: 
    llvm/test/CodeGen/PowerPC/aix-base-pointer.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 319cfac51035..2c95b97bafc1 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -73,10 +73,12 @@ static unsigned computeLinkageSize(const PPCSubtarget &STI) {
 }
 
 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
-  // SVR4 ABI: First slot in the general register save area.
-  return STI.isPPC64()
-             ? -16U
-             : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
+  // Third slot in the general purpose register save area.
+  if (STI.is32BitELFABI() && STI.getTargetMachine().isPositionIndependent())
+    return -12U;
+
+  // Second slot in the general purpose register save area.
+  return STI.isPPC64() ? -16U : -8U;
 }
 
 static unsigned computeCRSaveOffset(const PPCSubtarget &STI) {
@@ -2419,8 +2421,6 @@ unsigned PPCFrameLowering::getFramePointerSaveOffset() const {
 }
 
 unsigned PPCFrameLowering::getBasePointerSaveOffset() const {
-  if (Subtarget.isAIXABI())
-    report_fatal_error("BasePointer is not implemented on AIX yet.");
   return BasePointerSaveOffset;
 }
 

diff  --git a/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll b/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll
new file mode 100644
index 000000000000..2566e31c025d
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll
@@ -0,0 +1,42 @@
+; RUN: llc -mcpu=pwr7 -mattr=-altivec -verify-machineinstrs \
+; RUN:   -mtriple=powerpc-unknown-aix < %s  | FileCheck %s --check-prefix 32BIT
+
+; RUN: llc -mcpu=pwr7 -mattr=-altivec -verify-machineinstrs \
+; RUN:   -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix 64BIT
+
+; Use an overaligned buffer to force base-pointer usage. Test verifies:
+; - base pointer register (r30) is saved/defined/restored.
+; - stack frame is allocated with correct alignment.
+; - Address of %AlignedBuffer is calculated based off offset from the stack
+;   pointer.
+
+define void @caller() {
+  %AlignedBuffer = alloca [32 x i32], align 32
+  %Pointer = getelementptr inbounds [32 x i32], [32 x i32]* %AlignedBuffer, i64 0, i64 0
+  call void @callee(i32* %Pointer)
+  ret void
+}
+
+declare void @callee(i32*)
+
+; 32BIT-LABEL: .caller:
+; 32BIT:         stw 30, -8(1)
+; 32BIT:         mr 30, 1
+; 32BIT:         clrlwi  0, 1, 27
+; 32BIT:         subfic 0, 0, -224
+; 32BIT:         stwux 1, 1, 0
+; 32BIT:         addi 3, 1, 64
+; 32BIT:         bl .callee
+; 32BIT:         lwz 1, 0(1)
+; 32BIT:         lwz 30, -8(1)
+
+; 64BIT-LABEL: .caller:
+; 64BIT:         std 30, -16(1)
+; 64BIT:         mr 30, 1
+; 64BIT:         clrldi  0, 1, 59
+; 64BIT:         subfic 0, 0, -288
+; 64BIT:         stdux 1, 1, 0
+; 64BIT:         addi 3, 1, 128
+; 64BIT:         bl .callee
+; 64BIT:         ld 1, 0(1)
+; 64BIT:         ld 30, -16(1)