[PATCH] D83119: [Alignment][NFC] Use 5 bits to store Instructions Alignment
Guillaume Chatelet via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 3 01:35:22 PDT 2020
gchatelet created this revision.
gchatelet added a reviewer: courbet.
Herald added subscribers: llvm-commits, jfb, hiraditya.
Herald added a project: LLVM.
gchatelet edited the summary of this revision.
gchatelet updated this revision to Diff 275322.
gchatelet added a comment.
courbet accepted this revision.
This revision is now accepted and ready to land.
- Remove assert and move implementation in header
courbet added a comment.
Cool ! Only minor comments.
================
Comment at: llvm/include/llvm/IR/Instruction.h:61
+ template <unsigned Offset>
+ using BitfieldAlignmentElement =
+ typename Bitfield::Element<unsigned, Offset, 5,
----------------
[bikeshedding] Shouldn't that be `AlignmentBitfieldElement` ?
================
Comment at: llvm/include/llvm/IR/Instruction.h:59
+ // Template alias so that all Instruction storing alignment use the same
+ // definiton.
+ template <unsigned Offset>
----------------
Add comment: `// Align(1) is stored as 0. Valid alignments are powers of two from 2^0 to 2^MaxAlignmentExponent = 2^29, so we need 5 bits to encode the 30 possible values.`
As per MaxAlignmentExponent <https://github.com/llvm/llvm-project/blob/b7338fb1a6a464472850211165391983d2c8fdf3/llvm/include/llvm/IR/Value.h#L688> alignment is not allowed to be more than 2^29.
Encoded as Log2, this means that storing alignment uses 5 bits.
This patch makes sure all instructions store their alignment in a consistent way, encoded as Log2 and using 5 bits.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D83119
Files:
llvm/include/llvm/IR/Instruction.h
llvm/include/llvm/IR/Instructions.h
llvm/lib/IR/Instructions.cpp
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