[PATCH] D83052: [PowerPC][Power10] Add Vector Insert Instruction Definitions and MC Tests

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.

LGTM other than the naming nit.



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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:231
+// "/ UIM" (unused bit followed by a 4-bit immediate)
+class VXForm_VRT5_UIM5_RB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
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Since we are making the register constraints part of the instruction format, I think the name should reflect that.
Perhaps suffix these with `_ins` so that if we end up getting a non-destructive `VXForm` that takes a 5-bit unsigned immediate and a GPR and produces a VR, we won't use this form erroneously.


Repository:
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https://reviews.llvm.org/D83052