[PATCH] D83059: [RISCV] Use Generated Instruction Uncompresser

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: luismarques, asb.
Herald added subscribers: llvm-commits, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
lenary planned changes to this revision.
lenary added a comment.

Oh there's more to do, which may involve changes to `llvm/utils/TableGen/RISCVCompressInstEmitter.cpp`


This change allows `relaxInstruction` to use the auto-generated
instruction uncompression routine, rather than a partial implementation
of the same.

I am yet to find a testcase that this affects.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83059

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h


Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -23,6 +23,7 @@
 
 class RISCVAsmBackend : public MCAsmBackend {
   const MCSubtargetInfo &STI;
+  const MCRegisterInfo &MRI;
   uint8_t OSABI;
   bool Is64Bit;
   bool ForceRelocs = false;
@@ -30,10 +31,10 @@
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
 
 public:
-  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
-                  const MCTargetOptions &Options)
-      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
-        TargetOptions(Options) {
+  RISCVAsmBackend(const MCSubtargetInfo &STI, const MCRegisterInfo &MRI,
+                  uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)
+      : MCAsmBackend(support::little), STI(STI), MRI(MRI), OSABI(OSABI),
+        Is64Bit(Is64Bit), TargetOptions(Options) {
     TargetABI = RISCVABI::computeTargetABI(
         STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
     RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -23,6 +23,10 @@
 
 using namespace llvm;
 
+// Include the auto-generated portion of the compress emitter.
+#define GEN_UNCOMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
+
 Optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
   if (STI.getTargetTriple().isOSBinFormatELF()) {
     unsigned Type;
@@ -141,39 +145,11 @@
 
 void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
                                        const MCSubtargetInfo &STI) const {
-  // TODO: replace this with call to auto generated uncompressinstr() function.
-  MCInst Res;
-  switch (Inst.getOpcode()) {
-  default:
-    llvm_unreachable("Opcode not expected!");
-  case RISCV::C_BEQZ:
-    // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
-    Res.setOpcode(RISCV::BEQ);
-    Res.addOperand(Inst.getOperand(0));
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(1));
-    break;
-  case RISCV::C_BNEZ:
-    // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
-    Res.setOpcode(RISCV::BNE);
-    Res.addOperand(Inst.getOperand(0));
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(1));
-    break;
-  case RISCV::C_J:
-    // c.j $imm -> jal X0, $imm.
-    Res.setOpcode(RISCV::JAL);
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(0));
-    break;
-  case RISCV::C_JAL:
-    // c.jal $imm -> jal X1, $imm.
-    Res.setOpcode(RISCV::JAL);
-    Res.addOperand(MCOperand::createReg(RISCV::X1));
-    Res.addOperand(Inst.getOperand(0));
-    break;
-  }
-  Inst = std::move(Res);
+  bool Res;
+  MCInst UncompressedMI;
+  Res = uncompressInst(UncompressedMI, Inst, MRI, STI);
+  if (Res)
+    Inst = std::move(UncompressedMI);
 }
 
 // Given a compressed control flow instruction this function returns
@@ -472,5 +448,5 @@
                                           const MCTargetOptions &Options) {
   const Triple &TT = STI.getTargetTriple();
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
+  return new RISCVAsmBackend(STI, MRI, OSABI, TT.isArch64Bit(), Options);
 }


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