[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

[Albion Fung via Phabricator via llvm-commits]

Conanap marked 2 inline comments as done.
Conanap added a comment.

Addressed Anil's comments with regards to the test cases



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Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:56
+
+; CHECK: lxvrdx
+; Function Attrs: norecurse nounwind readonly
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anil9 wrote:
> I am not too familiar with the builtins but I never saw a check outside of the two braces in the test cases before,  is it not posible to include it inside the test cases ?
these were extra checks that I should've removed; thanks for catching it


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502