[PATCH] D83045: [AArch64][SVE] Add FP unpredicated to predicated two-op codegen

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr created this revision.
dancgr added reviewers: sdesmalen, efriedma, kmclaughlin, cameron.mcinally.
Herald added subscribers: llvm-commits, danielkiss, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.

This patch changes the predicated fmin, fmax, fminnm, fmaxnm from intrinsics to custom ISD nodes for lowering. These custom ISD nodes are then used to lower unpredicated versions of those instructions to be lowered to predicated ones.

I initially created an unpredicated intrinsic for this, because I didn't find any other way of generating the unpredicated fmin, fmax, etc. So I would appreciate any suggestions as to how to generate those unpredicated instructions without having to add more intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83045

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-fp-unpred-to-pred.ll

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