[llvm] dc8e4d8 - [ARM] Rearrange SizeReduction when using -Oz
Nicholas Guy via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 01:19:46 PDT 2020
Author: Nicholas Guy
Date: 2020-07-02T09:19:38+01:00
New Revision: dc8e4d856615806dc4c7bbd898cf0428b005e790
URL: https://github.com/llvm/llvm-project/commit/dc8e4d856615806dc4c7bbd898cf0428b005e790
DIFF: https://github.com/llvm/llvm-project/commit/dc8e4d856615806dc4c7bbd898cf0428b005e790.diff
LOG: [ARM] Rearrange SizeReduction when using -Oz
Move the Thumb2SizeReduce pass to before IfConversion when optimising
for minimal code size.
Running the Thumb2SizeReduction pass before IfConversionallows T1
instructions to propagate to the final output, rather than the
ifConverter modifying T2 instructions and preventing them from being
reduced later.
This change does introduce a regression regarding execution time, so
it's only applied when optimising for size.
Running the LLVM Test Suite with this change produces a geomean
difference of -0.1% for the size..text metric.
Differential Revision: https://reviews.llvm.org/D82439
Added:
Modified:
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
llvm/test/CodeGen/Thumb2/constant-hoisting.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 538ec446e0d8..9ead5fa4308c 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -518,9 +518,12 @@ void ARMPassConfig::addPreSched2() {
addPass(createARMExpandPseudoPass());
if (getOptLevel() != CodeGenOpt::None) {
- // in v8, IfConversion depends on Thumb instruction widths
+ // When optimising for size, always run the Thumb2SizeReduction pass before
+ // IfConversion. Otherwise, check whether IT blocks are restricted
+ // (e.g. in v8, IfConversion depends on Thumb instruction widths)
addPass(createThumb2SizeReductionPass([this](const Function &F) {
- return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
+ return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
+ this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
}));
addPass(createIfConverter([](const MachineFunction &MF) {
diff --git a/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll b/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
index e26f3848ddcd..e7b1780c5998 100644
--- a/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
+++ b/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
@@ -1,13 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7m--linux-gnu"
-; CHECK-LABEL: f:
-; CHECK: ldm r{{[0-9]}}!, {r[[x:[0-9]]]}
-; CHECK: add.w r[[x]], r[[x]], #3
-; CHECK: stm r{{[0-9]}}!, {r[[x]]}
+; NOTE: When optimising for minimum size, an LDM is expected to be generated
define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize minsize {
+; CHECK-LABEL: f:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: cmp r0, #1
+; CHECK-NEXT: blt .LBB0_2
+; CHECK-NEXT: .LBB0_1: @ %.lr.ph
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldm r2!, {r3}
+; CHECK-NEXT: adds r3, #3
+; CHECK-NEXT: stm r1!, {r3}
+; CHECK-NEXT: subs r0, #1
+; CHECK-NEXT: bne .LBB0_1
+; CHECK-NEXT: .LBB0_2: @ %._crit_edge
+; CHECK-NEXT: bx lr
%1 = icmp sgt i32 %n, 0
br i1 %1, label %.lr.ph, label %._crit_edge
@@ -28,9 +39,22 @@ define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize mi
ret void
}
-; CHECK-LABEL: f_nominsize:
-; CHECK-NOT: ldm
+; NOTE: When not optimising for minimum size, an LDM is expected not to be generated
define void @f_nominsize(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize {
+; CHECK-LABEL: f_nominsize:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: cmp r0, #1
+; CHECK-NEXT: it lt
+; CHECK-NEXT: bxlt lr
+; CHECK-NEXT: .LBB1_1: @ %.lr.ph
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldr r3, [r2], #4
+; CHECK-NEXT: subs r0, #1
+; CHECK-NEXT: add.w r3, r3, #3
+; CHECK-NEXT: str r3, [r1], #4
+; CHECK-NEXT: bne .LBB1_1
+; CHECK-NEXT: @ %bb.2: @ %._crit_edge
+; CHECK-NEXT: bx lr
%1 = icmp sgt i32 %n, 0
br i1 %1, label %.lr.ph, label %._crit_edge
diff --git a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
index a106900dc3e9..5c8f934ce61d 100644
--- a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
+++ b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
@@ -37,25 +37,26 @@ define i32 @test_values(i32 %a, i32 %b) minsize optsize {
; CHECK-V7M: mov r2, r0
; CHECK-V7M-NEXT: ldr r0, .LCPI0_0
; CHECK-V7M-NEXT: cmp r2, #50
-; CHECK-V7M-NEXT: beq .LBB0_3
+; CHECK-V7M-NEXT: beq .LBB0_5
; CHECK-V7M-NEXT: cmp r2, #1
-; CHECK-V7M-NEXT: ittt eq
-; CHECK-V7M-NEXT: addeq r0, r1
-; CHECK-V7M-NEXT: addeq r0, #1
-; CHECK-V7M-NEXT: bxeq lr
+; CHECK-V7M-NEXT: beq .LBB0_7
; CHECK-V7M-NEXT: cmp r2, #30
-; CHECK-V7M-NEXT: ittt eq
-; CHECK-V7M-NEXT: addeq r0, r1
-; CHECK-V7M-NEXT: addeq r0, #2
-; CHECK-V7M-NEXT: bxeq lr
-; CHECK-V7M-NEXT: cbnz r2, .LBB0_4
-; CHECK-V7M-NEXT: .LBB0_2:
+; CHECK-V7M-NEXT: beq .LBB0_8
+; CHECK-V7M-NEXT: cbnz r2, .LBB0_6
; CHECK-V7M-NEXT: add r0, r1
; CHECK-V7M-NEXT: bx lr
-; CHECK-V7M-NEXT: .LBB0_3:
+; CHECK-V7M-NEXT: .LBB0_5:
; CHECK-V7M-NEXT: add r0, r1
; CHECK-V7M-NEXT: adds r0, #4
-; CHECK-V7M-NEXT: .LBB0_4:
+; CHECK-V7M-NEXT: .LBB0_6:
+; CHECK-V7M-NEXT: bx lr
+; CHECK-V7M-NEXT: .LBB0_7:
+; CHECK-V7M-NEXT: add r0, r1
+; CHECK-V7M-NEXT: adds r0, #1
+; CHECK-V7M-NEXT: bx lr
+; CHECK-V7M-NEXT: .LBB0_8:
+; CHECK-V7M-NEXT: add r0, r1
+; CHECK-V7M-NEXT: adds r0, #2
; CHECK-V7M-NEXT: bx lr
; CHECK-V7M-NEXT: .p2align 2
; CHECK-V7M-NEXT: .LCPI0_0:
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