[PATCH] D82913: [RISCV] Add mcountinhibit CSR
Pengxuan Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 1 08:38:32 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd36f2c6a6c4b: [RISCV] Add mcountinhibit CSR (authored by pzheng).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82913/new/
https://reviews.llvm.org/D82913
Files:
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/machine-csr-names.s
Index: llvm/test/MC/RISCV/machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/machine-csr-names.s
+++ llvm/test/MC/RISCV/machine-csr-names.s
@@ -849,6 +849,20 @@
######################################
# Machine Counter Setup
######################################
+# mcountinhibit
+# name
+# CHECK-INST: csrrs t1, mcountinhibit, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x32]
+# CHECK-INST-ALIAS: csrr t1, mcountinhibit
+# uimm12
+# CHECK-INST: csrrs t2, mcountinhibit, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x32]
+# CHECK-INST-ALIAS: csrr t2, mcountinhibit
+# name
+csrrs t1, mcountinhibit, zero
+# uimm12
+csrrs t2, 0x320, zero
+
# mhpmevent3
# name
# CHECK-INST: csrrs t1, mhpmevent3, zero
Index: llvm/lib/Target/RISCV/RISCVSystemOperands.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -310,6 +310,7 @@
//===--------------------------
// Machine Counter Setup
//===--------------------------
+def : SysReg<"mcountinhibit", 0x320>;
def : SysReg<"mhpmevent3", 0x323>;
def : SysReg<"mhpmevent4", 0x324>;
def : SysReg<"mhpmevent5", 0x325>;
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