[llvm] d36f2c6 - [RISCV] Add mcountinhibit CSR

[Pengxuan Zheng via llvm-commits]

Author: Pengxuan Zheng
Date: 2020-07-01T08:27:00-07:00
New Revision: d36f2c6a6c4bb3c1cd213f3ed08a7a090fee54d2

URL: https://github.com/llvm/llvm-project/commit/d36f2c6a6c4bb3c1cd213f3ed08a7a090fee54d2
DIFF: https://github.com/llvm/llvm-project/commit/d36f2c6a6c4bb3c1cd213f3ed08a7a090fee54d2.diff

LOG: [RISCV] Add mcountinhibit CSR

Summary:
The mcountinhibit CSR is defined in the ratified 1.11 version of the privileged
spec.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82913

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSystemOperands.td
    llvm/test/MC/RISCV/machine-csr-names.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 47a1240cfaaf..8e75647bd4a9 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -310,6 +310,7 @@ def: SysReg<"mhpmcounter31h", 0xB9F>;
 //===--------------------------
 // Machine Counter Setup
 //===--------------------------
+def : SysReg<"mcountinhibit", 0x320>;
 def : SysReg<"mhpmevent3", 0x323>;
 def : SysReg<"mhpmevent4", 0x324>;
 def : SysReg<"mhpmevent5", 0x325>;

diff  --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index 6467b0493064..93ecd7e173ff 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -849,6 +849,20 @@ csrrs t2, 0xB1F, zero
 ######################################
 # Machine Counter Setup
 ######################################
+# mcountinhibit
+# name
+# CHECK-INST: csrrs t1, mcountinhibit, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x32]
+# CHECK-INST-ALIAS: csrr t1, mcountinhibit
+# uimm12
+# CHECK-INST: csrrs t2, mcountinhibit, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x32]
+# CHECK-INST-ALIAS: csrr t2, mcountinhibit
+# name
+csrrs t1, mcountinhibit, zero
+# uimm12
+csrrs t2, 0x320, zero
+
 # mhpmevent3
 # name
 # CHECK-INST: csrrs t1, mhpmevent3, zero