[PATCH] D82763: MIR: Infer not-SSA for subregister defs

[Francis Visoiu Mistrih via Phabricator via llvm-commits]

thegameg added inline comments.


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Comment at: llvm/include/llvm/CodeGen/MachineRegisterInfo.h:453
+  /// specified register, otherwise nullptr.
+  MachineOperand *getOneDef(Register Reg) const {
+    def_iterator DI = def_begin(Reg);
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There is a `MachineInstr *getUniqueVRegDef(Register Reg) const;`. Maybe name this one `getUniqueVRegDefOperand`? Are they actually vreg-only?


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  https://reviews.llvm.org/D82763/new/

https://reviews.llvm.org/D82763