[PATCH] D82440: [Power10] Implement Vector Shift Double Bit Immediate Builtins in LLVM/Clang

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.

The nits can be addressed on commit. I don't think another review is required. LGTM.



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Comment at: clang/lib/Headers/altivec.h:16887
+#define vec_sldb(__a, __b, __c)                                                \
+  _Generic((__a), vector signed char                                           \
+           : (vector signed char)__builtin_altivec_vsldbi(                     \
----------------
Do we need the macro overloading since nothing changes about the invocation? Can we not just:
```
#define vec_sldb(__a, __b, __c) \
  __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))
```


================
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:156
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_sldb(vsca, vscb, 0);
+  }
----------------
Maybe change one of these to pass a value larger than 7 to `vec_sldb` so that the truncation is shown.


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https://reviews.llvm.org/D82440