[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm updated this revision to Diff 274778.
paulwalker-arm marked an inline comment as done.
paulwalker-arm added a comment.

Updated selection comments to fully explain the rational.  Updated lowering code to be more caution in what is considered legal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll

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