[llvm] b485586 - [X86][SSE] Fix targetShrinkDemandedConstant constant vector sign extensions

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-07-01T12:12:53+01:00
New Revision: b485586482af213cf04a1e97712283db1707435b

URL: https://github.com/llvm/llvm-project/commit/b485586482af213cf04a1e97712283db1707435b
DIFF: https://github.com/llvm/llvm-project/commit/b485586482af213cf04a1e97712283db1707435b.diff

LOG: [X86][SSE] Fix targetShrinkDemandedConstant constant vector sign extensions

D82257/rG3521ecf1f8a3 was incorrectly sign-extending a constant vector from the lsb, this is fine if all the constant elements are 'allsignbits' in the active bits, but if only some of the elements are, then we are corrupting the constant values for those elements.

This fix ensures we sign extend from the msb of the active/demanded bits instead.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/shrink-const.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bf31e07029bb..bb4c28999e9d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33318,11 +33318,12 @@ X86TargetLowering::targetShrinkDemandedConstant(SDValue Op,
     if (EltSize > ActiveBits && EltSize > 1 && isTypeLegal(VT) &&
         (Opcode == ISD::OR || Opcode == ISD::XOR) &&
         NeedsSignExtension(Op.getOperand(1), ActiveBits)) {
-      EVT BoolVT = EVT::getVectorVT(*TLO.DAG.getContext(), MVT::i1,
+      EVT ExtSVT = EVT::getIntegerVT(*TLO.DAG.getContext(), ActiveBits);
+      EVT ExtVT = EVT::getVectorVT(*TLO.DAG.getContext(), ExtSVT,
                                     VT.getVectorNumElements());
       SDValue NewC =
           TLO.DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(Op), VT,
-                          Op.getOperand(1), TLO.DAG.getValueType(BoolVT));
+                          Op.getOperand(1), TLO.DAG.getValueType(ExtVT));
       SDValue NewOp =
           TLO.DAG.getNode(Opcode, SDLoc(Op), VT, Op.getOperand(0), NewC);
       return TLO.CombineTo(Op, NewOp);

diff  --git a/llvm/test/CodeGen/X86/shrink-const.ll b/llvm/test/CodeGen/X86/shrink-const.ll
index 32458afd4a9c..8502960f6e0d 100644
--- a/llvm/test/CodeGen/X86/shrink-const.ll
+++ b/llvm/test/CodeGen/X86/shrink-const.ll
@@ -2,19 +2,20 @@
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
 
-; FIXME: If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits
+; If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits
 define <4 x i32> @sext_vector_constants(<4 x i32> %a0) {
 ; SSE-LABEL: sext_vector_constants:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pslld $17, %xmm0
-; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
+; SSE-NEXT:    psrld $9, %xmm0
+; SSE-NEXT:    pxor {{.*}}(%rip), %xmm0
+; SSE-NEXT:    pslld $26, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: sext_vector_constants:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4227858432,4227858432,4227858432,4227858432]
-; AVX-NEXT:    vpslld $17, %xmm0, %xmm0
-; AVX-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpsrld $9, %xmm0, %xmm0
+; AVX-NEXT:    vpxor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:    vpslld $26, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9>
   %2 = xor <4 x i32> %1, <i32 314523200, i32 -2085372448, i32 144496960, i32 1532773600>