[PATCH] D82780: [AArch64][SVE] Put zeroing pseudos and patterns under flag.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen updated this revision to Diff 274723.
sdesmalen added a comment.

- Rebased patch, only zeroing forms are now predicated, (false lanes undef forms are now in separate multiclass)
- Some NFC changes while I was going through this file to clear up the meaning of things:
  - renamed `_zx` suffix of multiclasses to `_zeroing[_bhsd]`
  - Changed `isOrig` to `isReverseInstr`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82780/new/

https://reviews.llvm.org/D82780

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-merging.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-zeroing.ll

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