[PATCH] D82239: RISC-V machine attribute to disable floating-point division and square root instructions in codegen

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

My question is: why do we want this additional complexity? F and D both require FMUL/FDIV to be implemented, so saying you support F (and D) but no FMUL/FDIV is a contradiction, no such implementation can possibly exist (it would instead be say RV32I plus a non-standard extension that looks like a subset of the floating-point one). If you want to optimise for area, don't include an FPU, and if you want speed, include one, but this seems like a strange halfway house. Just because GCC has an option for something doesn't mean it makes sense for us to copy. What is your actual use case for this? Are there RISC-V implementations in the wild that do this and we're missing out on being able to target them, or is this just a hypothetical?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82239/new/

https://reviews.llvm.org/D82239