[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 30 14:41:36 PDT 2020


efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3244
+// NOTE: When targeting fixed length vectors at SVE the range of MVTs is runtime
+// variable, hence this manual selection.
+static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
----------------
paulwalker-arm wrote:
> efriedma wrote:
> > I'm not sure I understand the issue here. Is the problem just that for a pattern, you need to write the type of the result?  I don't think there's any problem with writing a pattern involving a type that isn't always legal; if the type isn't legal, it just won't match.
> I believe the issue is the runtime nature of the >128bit fixed length vectors means they are not mapped to any register class, which prevents pattern based matching.
> 
> We did investigate using hwmodes but it didn't prove to be a viable solution.
> I believe the issue is the runtime nature of the >128bit fixed length vectors means they are not mapped to any register class

You could change that in AArch64RegisterInfo.td, if you wanted to.  I don't think that would cause any issues; it's okay if some of the types in the list aren't legal for all subtargets.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871





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