[PATCH] D82792: [SVE][CodeGen] Legalisation of unpredicated load instructions

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2379
+    auto VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
+    auto VS1 = N1->getConstantOperandAPInt(0);
+    auto VS = DAG.getVScale(DL, VT, VS0 + VS1);
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kmclaughlin wrote:
> efriedma wrote:
> > Is there some reason to expect the two integers have the same width?
> I thought we could expect that the integers will have the same width here, since we're explicitly checking the opcodes used in the expression. I would have thought if the integers had different widths that the expression would also include a sign/zero extend or a truncate somewhere?
Both operands of an add have the same type as the result.  Not sure that says anything about the operands of the vscale operations: we don't enforce any rule there. If it's supposed to be the same as the result type, probably SelectionDAG::getNode() should check that.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82792/new/

https://reviews.llvm.org/D82792