[llvm] a7b0f39 - [MVT] Add new MVT types for RISC-V vector.
Hsiangkai Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 10:08:06 PDT 2020
Author: Hsiangkai Wang
Date: 2020-07-01T01:07:50+08:00
New Revision: a7b0f391852b6dd9001b5247269612b3d2c3ce31
URL: https://github.com/llvm/llvm-project/commit/a7b0f391852b6dd9001b5247269612b3d2c3ce31
DIFF: https://github.com/llvm/llvm-project/commit/a7b0f391852b6dd9001b5247269612b3d2c3ce31.diff
LOG: [MVT] Add new MVT types for RISC-V vector.
In RISC-V vector extension, users could group multiple vector registers
as one pseudo register. In mixed width operations, users could use
partial vector registers to reduce the register pressure. The parameter
to control register grouping and partial use is called LMUL. LMUL is a
part of the type. So, we have a bunch of vector types. In order to
support all these types, we need new MVT types in LLVM. In this patch, I
added several MVT types that are used in RISC-V vector implementation.
This is a standalone patch for MVT types without RISC-V related implementation.
Differential revision: https://reviews.llvm.org/D81724
Added:
Modified:
llvm/include/llvm/CodeGen/ValueTypes.td
llvm/include/llvm/Support/MachineValueType.h
llvm/lib/CodeGen/ValueTypes.cpp
llvm/utils/TableGen/CodeGenTarget.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index dfa2e81608be..c5eb87cf1d34 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -133,56 +133,62 @@ def nxv4i1 : ValueType<4, 103>; // n x 4 x i1 vector value
def nxv8i1 : ValueType<8, 104>; // n x 8 x i1 vector value
def nxv16i1 : ValueType<16, 105>; // n x 16 x i1 vector value
def nxv32i1 : ValueType<32, 106>; // n x 32 x i1 vector value
+def nxv64i1 : ValueType<64,107>; // n x 64 x i1 vector value
+
+def nxv1i8 : ValueType<8, 108>; // n x 1 x i8 vector value
+def nxv2i8 : ValueType<16, 109>; // n x 2 x i8 vector value
+def nxv4i8 : ValueType<32, 110>; // n x 4 x i8 vector value
+def nxv8i8 : ValueType<64, 111>; // n x 8 x i8 vector value
+def nxv16i8 : ValueType<128, 112>; // n x 16 x i8 vector value
+def nxv32i8 : ValueType<256, 113>; // n x 32 x i8 vector value
+def nxv64i8 : ValueType<512, 114>; // n x 64 x i8 vector value
+
+def nxv1i16 : ValueType<16, 115>; // n x 1 x i16 vector value
+def nxv2i16 : ValueType<32, 116>; // n x 2 x i16 vector value
+def nxv4i16 : ValueType<64, 117>; // n x 4 x i16 vector value
+def nxv8i16 : ValueType<128, 118>; // n x 8 x i16 vector value
+def nxv16i16: ValueType<256, 119>; // n x 16 x i16 vector value
+def nxv32i16: ValueType<512, 120>; // n x 32 x i16 vector value
+
+def nxv1i32 : ValueType<32, 121>; // n x 1 x i32 vector value
+def nxv2i32 : ValueType<64, 122>; // n x 2 x i32 vector value
+def nxv4i32 : ValueType<128, 123>; // n x 4 x i32 vector value
+def nxv8i32 : ValueType<256, 124>; // n x 8 x i32 vector value
+def nxv16i32: ValueType<512, 125>; // n x 16 x i32 vector value
+def nxv32i32: ValueType<1024,126>; // n x 32 x i32 vector value
+
+def nxv1i64 : ValueType<64, 127>; // n x 1 x i64 vector value
+def nxv2i64 : ValueType<128, 128>; // n x 2 x i64 vector value
+def nxv4i64 : ValueType<256, 129>; // n x 4 x i64 vector value
+def nxv8i64 : ValueType<512, 130>; // n x 8 x i64 vector value
+def nxv16i64: ValueType<1024,131>; // n x 16 x i64 vector value
+def nxv32i64: ValueType<2048,132>; // n x 32 x i64 vector value
+
+def nxv1f16 : ValueType<32, 133>; // n x 1 x f16 vector value
+def nxv2f16 : ValueType<32 , 134>; // n x 2 x f16 vector value
+def nxv4f16 : ValueType<64 , 135>; // n x 4 x f16 vector value
+def nxv8f16 : ValueType<128, 136>; // n x 8 x f16 vector value
+def nxv16f16 : ValueType<256,137>; // n x 16 x f16 vector value
+def nxv32f16 : ValueType<512,138>; // n x 32 x f16 vector value
+def nxv2bf16 : ValueType<32 , 139>; // n x 2 x bf16 vector value
+def nxv4bf16 : ValueType<64 , 140>; // n x 4 x bf16 vector value
+def nxv8bf16 : ValueType<128, 141>; // n x 8 x bf16 vector value
+def nxv1f32 : ValueType<32 , 142>; // n x 1 x f32 vector value
+def nxv2f32 : ValueType<64 , 143>; // n x 2 x f32 vector value
+def nxv4f32 : ValueType<128, 144>; // n x 4 x f32 vector value
+def nxv8f32 : ValueType<256, 145>; // n x 8 x f32 vector value
+def nxv16f32 : ValueType<512, 146>; // n x 16 x f32 vector value
+def nxv1f64 : ValueType<64, 147>; // n x 1 x f64 vector value
+def nxv2f64 : ValueType<128, 148>; // n x 2 x f64 vector value
+def nxv4f64 : ValueType<256, 149>; // n x 4 x f64 vector value
+def nxv8f64 : ValueType<512, 150>; // n x 8 x f64 vector value
+
+def x86mmx : ValueType<64 , 151>; // X86 MMX value
+def FlagVT : ValueType<0 , 152>; // Pre-RA sched glue
+def isVoid : ValueType<0 , 153>; // Produces no value
+def untyped: ValueType<8 , 154>; // Produces an untyped value
+def exnref : ValueType<0 , 155>; // WebAssembly's exnref type
-def nxv1i8 : ValueType<8, 107>; // n x 1 x i8 vector value
-def nxv2i8 : ValueType<16, 108>; // n x 2 x i8 vector value
-def nxv4i8 : ValueType<32, 109>; // n x 4 x i8 vector value
-def nxv8i8 : ValueType<64, 110>; // n x 8 x i8 vector value
-def nxv16i8 : ValueType<128, 111>; // n x 16 x i8 vector value
-def nxv32i8 : ValueType<256, 112>; // n x 32 x i8 vector value
-
-def nxv1i16 : ValueType<16, 113>; // n x 1 x i16 vector value
-def nxv2i16 : ValueType<32, 114>; // n x 2 x i16 vector value
-def nxv4i16 : ValueType<64, 115>; // n x 4 x i16 vector value
-def nxv8i16 : ValueType<128, 116>; // n x 8 x i16 vector value
-def nxv16i16: ValueType<256, 117>; // n x 16 x i16 vector value
-def nxv32i16: ValueType<512, 118>; // n x 32 x i16 vector value
-
-def nxv1i32 : ValueType<32, 119>; // n x 1 x i32 vector value
-def nxv2i32 : ValueType<64, 120>; // n x 2 x i32 vector value
-def nxv4i32 : ValueType<128, 121>; // n x 4 x i32 vector value
-def nxv8i32 : ValueType<256, 122>; // n x 8 x i32 vector value
-def nxv16i32: ValueType<512, 123>; // n x 16 x i32 vector value
-def nxv32i32: ValueType<1024,124>; // n x 32 x i32 vector value
-
-def nxv1i64 : ValueType<64, 125>; // n x 1 x i64 vector value
-def nxv2i64 : ValueType<128, 126>; // n x 2 x i64 vector value
-def nxv4i64 : ValueType<256, 127>; // n x 4 x i64 vector value
-def nxv8i64 : ValueType<512, 128>; // n x 8 x i64 vector value
-def nxv16i64: ValueType<1024,129>; // n x 16 x i64 vector value
-def nxv32i64: ValueType<2048,130>; // n x 32 x i64 vector value
-
-def nxv2f16 : ValueType<32 , 131>; // n x 2 x f16 vector value
-def nxv4f16 : ValueType<64 , 132>; // n x 4 x f16 vector value
-def nxv8f16 : ValueType<128, 133>; // n x 8 x f16 vector value
-def nxv2bf16 : ValueType<32 , 134>; // n x 2 x bf16 vector value
-def nxv4bf16 : ValueType<64 , 135>; // n x 4 x bf16 vector value
-def nxv8bf16 : ValueType<128, 136>; // n x 8 x bf16 vector value
-def nxv1f32 : ValueType<32 , 137>; // n x 1 x f32 vector value
-def nxv2f32 : ValueType<64 , 138>; // n x 2 x f32 vector value
-def nxv4f32 : ValueType<128, 139>; // n x 4 x f32 vector value
-def nxv8f32 : ValueType<256, 140>; // n x 8 x f32 vector value
-def nxv16f32 : ValueType<512, 141>; // n x 16 x f32 vector value
-def nxv1f64 : ValueType<64, 142>; // n x 1 x f64 vector value
-def nxv2f64 : ValueType<128, 143>; // n x 2 x f64 vector value
-def nxv4f64 : ValueType<256, 144>; // n x 4 x f64 vector value
-def nxv8f64 : ValueType<512, 145>; // n x 8 x f64 vector value
-
-def x86mmx : ValueType<64 , 146>; // X86 MMX value
-def FlagVT : ValueType<0 , 147>; // Pre-RA sched glue
-def isVoid : ValueType<0 , 148>; // Produces no value
-def untyped: ValueType<8 , 149>; // Produces an untyped value
-def exnref : ValueType<0 , 150>; // WebAssembly's exnref type
def token : ValueType<0 , 248>; // TokenTy
def MetadataVT: ValueType<0, 249>; // Metadata
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
index e87891586875..3bb8220e72e5 100644
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -166,55 +166,60 @@ namespace llvm {
nxv8i1 = 104, // n x 8 x i1
nxv16i1 = 105, // n x 16 x i1
nxv32i1 = 106, // n x 32 x i1
-
- nxv1i8 = 107, // n x 1 x i8
- nxv2i8 = 108, // n x 2 x i8
- nxv4i8 = 109, // n x 4 x i8
- nxv8i8 = 110, // n x 8 x i8
- nxv16i8 = 111, // n x 16 x i8
- nxv32i8 = 112, // n x 32 x i8
-
- nxv1i16 = 113, // n x 1 x i16
- nxv2i16 = 114, // n x 2 x i16
- nxv4i16 = 115, // n x 4 x i16
- nxv8i16 = 116, // n x 8 x i16
- nxv16i16 = 117, // n x 16 x i16
- nxv32i16 = 118, // n x 32 x i16
-
- nxv1i32 = 119, // n x 1 x i32
- nxv2i32 = 120, // n x 2 x i32
- nxv4i32 = 121, // n x 4 x i32
- nxv8i32 = 122, // n x 8 x i32
- nxv16i32 = 123, // n x 16 x i32
- nxv32i32 = 124, // n x 32 x i32
-
- nxv1i64 = 125, // n x 1 x i64
- nxv2i64 = 126, // n x 2 x i64
- nxv4i64 = 127, // n x 4 x i64
- nxv8i64 = 128, // n x 8 x i64
- nxv16i64 = 129, // n x 16 x i64
- nxv32i64 = 130, // n x 32 x i64
+ nxv64i1 = 107, // n x 64 x i1
+
+ nxv1i8 = 108, // n x 1 x i8
+ nxv2i8 = 109, // n x 2 x i8
+ nxv4i8 = 110, // n x 4 x i8
+ nxv8i8 = 111, // n x 8 x i8
+ nxv16i8 = 112, // n x 16 x i8
+ nxv32i8 = 113, // n x 32 x i8
+ nxv64i8 = 114, // n x 64 x i8
+
+ nxv1i16 = 115, // n x 1 x i16
+ nxv2i16 = 116, // n x 2 x i16
+ nxv4i16 = 117, // n x 4 x i16
+ nxv8i16 = 118, // n x 8 x i16
+ nxv16i16 = 119, // n x 16 x i16
+ nxv32i16 = 120, // n x 32 x i16
+
+ nxv1i32 = 121, // n x 1 x i32
+ nxv2i32 = 122, // n x 2 x i32
+ nxv4i32 = 123, // n x 4 x i32
+ nxv8i32 = 124, // n x 8 x i32
+ nxv16i32 = 125, // n x 16 x i32
+ nxv32i32 = 126, // n x 32 x i32
+
+ nxv1i64 = 127, // n x 1 x i64
+ nxv2i64 = 128, // n x 2 x i64
+ nxv4i64 = 129, // n x 4 x i64
+ nxv8i64 = 130, // n x 8 x i64
+ nxv16i64 = 131, // n x 16 x i64
+ nxv32i64 = 132, // n x 32 x i64
FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
- nxv2f16 = 131, // n x 2 x f16
- nxv4f16 = 132, // n x 4 x f16
- nxv8f16 = 133, // n x 8 x f16
- nxv2bf16 = 134, // n x 2 x bf16
- nxv4bf16 = 135, // n x 4 x bf16
- nxv8bf16 = 136, // n x 8 x bf16
- nxv1f32 = 137, // n x 1 x f32
- nxv2f32 = 138, // n x 2 x f32
- nxv4f32 = 139, // n x 4 x f32
- nxv8f32 = 140, // n x 8 x f32
- nxv16f32 = 141, // n x 16 x f32
- nxv1f64 = 142, // n x 1 x f64
- nxv2f64 = 143, // n x 2 x f64
- nxv4f64 = 144, // n x 4 x f64
- nxv8f64 = 145, // n x 8 x f64
-
- FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv2f16,
+ nxv1f16 = 133, // n x 1 x f16
+ nxv2f16 = 134, // n x 2 x f16
+ nxv4f16 = 135, // n x 4 x f16
+ nxv8f16 = 136, // n x 8 x f16
+ nxv16f16 = 137, // n x 16 x f16
+ nxv32f16 = 138, // n x 32 x f16
+ nxv2bf16 = 139, // n x 2 x bf16
+ nxv4bf16 = 140, // n x 4 x bf16
+ nxv8bf16 = 141, // n x 8 x bf16
+ nxv1f32 = 142, // n x 1 x f32
+ nxv2f32 = 143, // n x 2 x f32
+ nxv4f32 = 144, // n x 4 x f32
+ nxv8f32 = 145, // n x 8 x f32
+ nxv16f32 = 146, // n x 16 x f32
+ nxv1f64 = 147, // n x 1 x f64
+ nxv2f64 = 148, // n x 2 x f64
+ nxv4f64 = 149, // n x 4 x f64
+ nxv8f64 = 150, // n x 8 x f64
+
+ FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
@@ -223,20 +228,20 @@ namespace llvm {
FIRST_VECTOR_VALUETYPE = v1i1,
LAST_VECTOR_VALUETYPE = nxv8f64,
- x86mmx = 146, // This is an X86 MMX value
+ x86mmx = 151, // This is an X86 MMX value
- Glue = 147, // This glues nodes together during pre-RA sched
+ Glue = 152, // This glues nodes together during pre-RA sched
- isVoid = 148, // This has no value
+ isVoid = 153, // This has no value
- Untyped = 149, // This value takes a register, but has
+ Untyped = 154, // This value takes a register, but has
// unspecified type. The register class
// will be determined by the opcode.
- exnref = 150, // WebAssembly's exnref type
+ exnref = 155, // WebAssembly's exnref type
FIRST_VALUETYPE = 1, // This is always the beginning of the list.
- LAST_VALUETYPE = 151, // This always remains at the end of the list.
+ LAST_VALUETYPE = 156, // This always remains at the end of the list.
// This is the current maximum for LAST_VALUETYPE.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
@@ -409,9 +414,9 @@ namespace llvm {
/// Return true if this is an overloaded type for TableGen.
bool isOverloaded() const {
- return (SimpleTy==MVT::Any ||
- SimpleTy==MVT::iAny || SimpleTy==MVT::fAny ||
- SimpleTy==MVT::vAny || SimpleTy==MVT::iPTRAny);
+ return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
+ SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
+ SimpleTy == MVT::iPTRAny);
}
/// Return a VT for a vector type with the same element type but
@@ -465,7 +470,8 @@ namespace llvm {
case nxv4i1:
case nxv8i1:
case nxv16i1:
- case nxv32i1: return i1;
+ case nxv32i1:
+ case nxv64i1: return i1;
case v1i8:
case v2i8:
case v4i8:
@@ -480,7 +486,8 @@ namespace llvm {
case nxv4i8:
case nxv8i8:
case nxv16i8:
- case nxv32i8: return i8;
+ case nxv32i8:
+ case nxv64i8: return i8;
case v1i16:
case v2i16:
case v3i16:
@@ -537,9 +544,12 @@ namespace llvm {
case v32f16:
case v64f16:
case v128f16:
+ case nxv1f16:
case nxv2f16:
case nxv4f16:
- case nxv8f16: return f16;
+ case nxv8f16:
+ case nxv16f16:
+ case nxv32f16: return f16;
case v2bf16:
case v3bf16:
case v4bf16:
@@ -612,7 +622,9 @@ namespace llvm {
case v64i32:
case v64f16:
case v64bf16:
- case v64f32: return 64;
+ case v64f32:
+ case nxv64i1:
+ case nxv64i8: return 64;
case v32i1:
case v32i8:
case v32i16:
@@ -626,7 +638,8 @@ namespace llvm {
case nxv32i8:
case nxv32i16:
case nxv32i32:
- case nxv32i64: return 32;
+ case nxv32i64:
+ case nxv32f16: return 32;
case v16i1:
case v16i8:
case v16i16:
@@ -641,6 +654,7 @@ namespace llvm {
case nxv16i16:
case nxv16i32:
case nxv16i64:
+ case nxv16f16:
case nxv16f32: return 16;
case v8i1:
case v8i8:
@@ -716,6 +730,7 @@ namespace llvm {
case nxv1i16:
case nxv1i32:
case nxv1i64:
+ case nxv1f16:
case nxv1f32:
case nxv1f64: return 1;
}
@@ -774,7 +789,8 @@ namespace llvm {
case v1i16: return TypeSize::Fixed(16);
case nxv16i1:
case nxv2i8:
- case nxv1i16: return TypeSize::Scalable(16);
+ case nxv1i16:
+ case nxv1f16: return TypeSize::Scalable(16);
case f32 :
case i32 :
case v32i1:
@@ -806,6 +822,7 @@ namespace llvm {
case v4bf16:
case v2f32:
case v1f64: return TypeSize::Fixed(64);
+ case nxv64i1:
case nxv8i8:
case nxv4i16:
case nxv2i32:
@@ -853,6 +870,7 @@ namespace llvm {
case nxv16i16:
case nxv8i32:
case nxv4i64:
+ case nxv16f16:
case nxv8f32:
case nxv4f64: return TypeSize::Scalable(256);
case v512i1:
@@ -864,9 +882,11 @@ namespace llvm {
case v32bf16:
case v16f32:
case v8f64: return TypeSize::Fixed(512);
+ case nxv64i8:
case nxv32i16:
case nxv16i32:
case nxv8i64:
+ case nxv32f16:
case nxv16f32:
case nxv8f64: return TypeSize::Scalable(512);
case v1024i1:
@@ -1115,6 +1135,7 @@ namespace llvm {
if (NumElements == 8) return MVT::nxv8i1;
if (NumElements == 16) return MVT::nxv16i1;
if (NumElements == 32) return MVT::nxv32i1;
+ if (NumElements == 64) return MVT::nxv64i1;
break;
case MVT::i8:
if (NumElements == 1) return MVT::nxv1i8;
@@ -1123,6 +1144,7 @@ namespace llvm {
if (NumElements == 8) return MVT::nxv8i8;
if (NumElements == 16) return MVT::nxv16i8;
if (NumElements == 32) return MVT::nxv32i8;
+ if (NumElements == 64) return MVT::nxv64i8;
break;
case MVT::i16:
if (NumElements == 1) return MVT::nxv1i16;
@@ -1149,9 +1171,12 @@ namespace llvm {
if (NumElements == 32) return MVT::nxv32i64;
break;
case MVT::f16:
+ if (NumElements == 1) return MVT::nxv1f16;
if (NumElements == 2) return MVT::nxv2f16;
if (NumElements == 4) return MVT::nxv4f16;
if (NumElements == 8) return MVT::nxv8f16;
+ if (NumElements == 16) return MVT::nxv16f16;
+ if (NumElements == 32) return MVT::nxv32f16;
break;
case MVT::bf16:
if (NumElements == 2) return MVT::nxv2bf16;
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index 68e8acd218ba..2ff596629a7e 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -371,6 +371,8 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
return ScalableVectorType::get(Type::getInt1Ty(Context), 16);
case MVT::nxv32i1:
return ScalableVectorType::get(Type::getInt1Ty(Context), 32);
+ case MVT::nxv64i1:
+ return ScalableVectorType::get(Type::getInt1Ty(Context), 64);
case MVT::nxv1i8:
return ScalableVectorType::get(Type::getInt8Ty(Context), 1);
case MVT::nxv2i8:
@@ -383,6 +385,8 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
return ScalableVectorType::get(Type::getInt8Ty(Context), 16);
case MVT::nxv32i8:
return ScalableVectorType::get(Type::getInt8Ty(Context), 32);
+ case MVT::nxv64i8:
+ return ScalableVectorType::get(Type::getInt8Ty(Context), 64);
case MVT::nxv1i16:
return ScalableVectorType::get(Type::getInt16Ty(Context), 1);
case MVT::nxv2i16:
@@ -419,12 +423,18 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
return ScalableVectorType::get(Type::getInt64Ty(Context), 16);
case MVT::nxv32i64:
return ScalableVectorType::get(Type::getInt64Ty(Context), 32);
+ case MVT::nxv1f16:
+ return ScalableVectorType::get(Type::getHalfTy(Context), 1);
case MVT::nxv2f16:
return ScalableVectorType::get(Type::getHalfTy(Context), 2);
case MVT::nxv4f16:
return ScalableVectorType::get(Type::getHalfTy(Context), 4);
case MVT::nxv8f16:
return ScalableVectorType::get(Type::getHalfTy(Context), 8);
+ case MVT::nxv16f16:
+ return ScalableVectorType::get(Type::getHalfTy(Context), 16);
+ case MVT::nxv32f16:
+ return ScalableVectorType::get(Type::getHalfTy(Context), 32);
case MVT::nxv2bf16:
return ScalableVectorType::get(Type::getBFloatTy(Context), 2);
case MVT::nxv4bf16:
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 3b53a8531d3f..891a08ea590e 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -169,12 +169,14 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
case MVT::nxv8i1: return "MVT::nxv8i1";
case MVT::nxv16i1: return "MVT::nxv16i1";
case MVT::nxv32i1: return "MVT::nxv32i1";
+ case MVT::nxv64i1: return "MVT::nxv64i1";
case MVT::nxv1i8: return "MVT::nxv1i8";
case MVT::nxv2i8: return "MVT::nxv2i8";
case MVT::nxv4i8: return "MVT::nxv4i8";
case MVT::nxv8i8: return "MVT::nxv8i8";
case MVT::nxv16i8: return "MVT::nxv16i8";
case MVT::nxv32i8: return "MVT::nxv32i8";
+ case MVT::nxv64i8: return "MVT::nxv64i8";
case MVT::nxv1i16: return "MVT::nxv1i16";
case MVT::nxv2i16: return "MVT::nxv2i16";
case MVT::nxv4i16: return "MVT::nxv4i16";
@@ -186,14 +188,19 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
case MVT::nxv4i32: return "MVT::nxv4i32";
case MVT::nxv8i32: return "MVT::nxv8i32";
case MVT::nxv16i32: return "MVT::nxv16i32";
+ case MVT::nxv32i32: return "MVT::nxv32i32";
case MVT::nxv1i64: return "MVT::nxv1i64";
case MVT::nxv2i64: return "MVT::nxv2i64";
case MVT::nxv4i64: return "MVT::nxv4i64";
case MVT::nxv8i64: return "MVT::nxv8i64";
case MVT::nxv16i64: return "MVT::nxv16i64";
+ case MVT::nxv32i64: return "MVT::nxv32i64";
+ case MVT::nxv1f16: return "MVT::nxv1f16";
case MVT::nxv2f16: return "MVT::nxv2f16";
case MVT::nxv4f16: return "MVT::nxv4f16";
case MVT::nxv8f16: return "MVT::nxv8f16";
+ case MVT::nxv16f16: return "MVT::nxv16f16";
+ case MVT::nxv32f16: return "MVT::nxv32f16";
case MVT::nxv2bf16: return "MVT::nxv2bf16";
case MVT::nxv4bf16: return "MVT::nxv4bf16";
case MVT::nxv8bf16: return "MVT::nxv8bf16";
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