[llvm] 3324e3a - [ARM] Allow the fabs intrinsic to be tail predicated

[Samuel Tebbs via llvm-commits]

Author: Samuel Tebbs
Date: 2020-06-30T17:27:28+01:00
New Revision: 3324e3a6eeb5aab8b704509bb4b40e652da3799d

URL: https://github.com/llvm/llvm-project/commit/3324e3a6eeb5aab8b704509bb4b40e652da3799d
DIFF: https://github.com/llvm/llvm-project/commit/3324e3a6eeb5aab8b704509bb4b40e652da3799d.diff

LOG: [ARM] Allow the fabs intrinsic to be tail predicated

This patch stops the fabs intrinsic from blocking tail predication.

Differential Revision: https://reviews.llvm.org/D82570

Added: 
    llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll

Modified: 
    llvm/lib/Target/ARM/MVETailPredication.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp
index 4bb60701ce5e..6583dcb77e1e 100644
--- a/llvm/lib/Target/ARM/MVETailPredication.cpp
+++ b/llvm/lib/Target/ARM/MVETailPredication.cpp
@@ -254,6 +254,7 @@ bool MVETailPredication::IsPredicatedVectorLoop() {
       case Intrinsic::round:
       case Intrinsic::floor:
       case Intrinsic::ceil:
+      case Intrinsic::fabs:
         if (ST->hasMVEFloatOps())
           continue;
         LLVM_FALLTHROUGH;

diff  --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
new file mode 100644
index 000000000000..d3247a3fd28e
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s
+define arm_aapcs_vfpcc void @fabs(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %blockSize) {
+; CHECK-LABEL: fabs:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r7, lr}
+; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    cmp r2, #0
+; CHECK-NEXT:    it eq
+; CHECK-NEXT:    popeq {r7, pc}
+; CHECK-NEXT:    dlstp.32 lr, r2
+; CHECK-NEXT:  .LBB0_1: @ %vector.body
+; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
+; CHECK-NEXT:    vabs.f32 q0, q0
+; CHECK-NEXT:    vstrw.32 q0, [r1], #16
+; CHECK-NEXT:    letp lr, .LBB0_1
+; CHECK-NEXT:  @ %bb.2: @ %while.end
+; CHECK-NEXT:    pop {r7, pc}
+entry:
+  %cmp3 = icmp eq i32 %blockSize, 0
+  br i1 %cmp3, label %while.end, label %vector.ph
+
+vector.ph:                                        ; preds = %entry
+  %n.rnd.up = add i32 %blockSize, 3
+  %n.vec = and i32 %n.rnd.up, -4
+  %trip.count.minus.1 = add i32 %blockSize, -1
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %next.gep = getelementptr float, float* %pDst, i32 %index
+  %next.gep13 = getelementptr float, float* %pSrcA, i32 %index
+  %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
+  %0 = bitcast float* %next.gep13 to <4 x float>*
+  %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
+  %1 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.masked.load)
+  %2 = bitcast float* %next.gep to <4 x float>*
+  call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
+  %index.next = add i32 %index, 4
+  %3 = icmp eq i32 %index.next, %n.vec
+  br i1 %3, label %while.end, label %vector.body
+
+while.end:                                        ; preds = %vector.body, %entry
+  ret void
+}
+
+declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
+
+declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
+
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
+
+declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)