[PATCH] D82859: [Power10] Implement VSX vector permute extended instruction

[Biplob Mishra via Phabricator via llvm-commits]

biplmish created this revision.
biplmish added reviewers: nemanjai, amyk, PowerPC.
Herald added subscribers: wuzish, kbarton, hiraditya.
Herald added a project: LLVM.

This patch implements the below vector permute extended instruction on Power10.

xxpermx XT,XA,XB,XC,UIM


https://reviews.llvm.org/D82859

Files:
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s


Index: llvm/test/MC/PowerPC/p10.s
===================================================================
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -33,3 +33,8 @@
 # CHECK-BE: vclrrb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3                        # encoding: [0xcd,0x19,0x24,0x10]
             vclrrb 1, 4, 3
+# CHECK-BE: xxpermx 6, 63, 21, 34, 2              # encoding: [0x05,0x00,0x00,0x02,
+# CHECK-BE-SAME:                                               0x88,0xdf,0xa8,0x8c]
+# CHECK-LE: xxpermx 6, 63, 21, 34, 2              # encoding: [0x02,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0x8c,0xa8,0xdf,0x88]
+            xxpermx 6, 63, 21, 34, 2
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -30,3 +30,6 @@
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# CHECK: xxpermx 6, 63, 21, 34, 2
+0x05 0x00 0x00 0x02 0x88 0xdf 0xa8 0x8c
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -177,6 +177,38 @@
   let Inst{31} = XT{5};
 }
 
+// 8RR:XX4-form.
+class 8RR_XX4_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 
+                          string asmstr, InstrItinClass itin,
+                          list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XA;
+  bits<6> XB;
+  bits<6> XC;
+  bits<3> IMM; 
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1; 
+  let Inst{8-11} = 0; 
+  let Inst{12-13} = 0; 
+  let Inst{14-28} = 0; 
+  let Inst{29-31} = IMM; 
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-47} = XA{4-0};
+  let Inst{48-52} = XB{4-0};
+  let Inst{53-57} = XC{4-0};
+  let Inst{58-59} = xo;
+  let Inst{60} = XC{5};
+  let Inst{61} = XA{5};
+  let Inst{62} = XB{5};
+  let Inst{63} = XT{5};
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
                                        dag PCRel_IOL, string asmstr,
                                        InstrItinClass itin> {
@@ -517,6 +549,14 @@
   def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
 }
 
+let Predicates = [PrefixInstrs] in {
+  def XXPERMX :
+    8RR_XX4_IMM3_XTABC6<34, 0, (outs vsrc:$XT),
+                        (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u3imm:$UIM),
+                        "xxpermx $XT, $XA, $XB, $XC, $UIM",
+                        IIC_VecPerm, []>;
+}
+
 let Predicates = [IsISA3_1] in {
    def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpdepd $vD, $vA, $vB", IIC_VecGeneral,


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