[llvm] 5f8bdb3 - [Alignment][NFC] TargetLowering::allowsMemoryAccess
Guillaume Chatelet via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 01:17:14 PDT 2020
Author: Guillaume Chatelet
Date: 2020-06-30T08:17:00Z
New Revision: 5f8bdb3e6a997a3031a447db38bd3c358fee86e4
URL: https://github.com/llvm/llvm-project/commit/5f8bdb3e6a997a3031a447db38bd3c358fee86e4
DIFF: https://github.com/llvm/llvm-project/commit/5f8bdb3e6a997a3031a447db38bd3c358fee86e4.diff
LOG: [Alignment][NFC] TargetLowering::allowsMemoryAccess
Second patch of a series to adapt TargetLowering::allowsXXX functions
This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Differential Revision: https://reviews.llvm.org/D82785
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.h
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index bbc507e23098..827845fd2162 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1613,7 +1613,7 @@ class TargetLoweringBase {
/// target).
virtual bool
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
- unsigned AddrSpace = 0, unsigned Alignment = 1,
+ unsigned AddrSpace = 0, Align Alignment = Align(1),
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool *Fast = nullptr) const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2568f66bf4fc..f96907100a88 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4881,7 +4881,7 @@ bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
const Align LDSTAlign = LDST->getAlign();
const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt);
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
- LDST->getAddressSpace(), NarrowAlign.value(),
+ LDST->getAddressSpace(), NarrowAlign,
LDST->getMemOperand()->getFlags()))
return false;
}
@@ -8498,7 +8498,7 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) {
SDLoc DL(RHS);
uint64_t PtrOff =
IsFSHL ? (((BitWidth - ShAmt) % BitWidth) / 8) : (ShAmt / 8);
- unsigned NewAlign = MinAlign(RHS->getAlignment(), PtrOff);
+ Align NewAlign = commonAlignment(RHS->getAlign(), PtrOff);
bool Fast = false;
if (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
RHS->getAddressSpace(), NewAlign,
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index c8220928af93..bcb2083c4f73 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1599,19 +1599,21 @@ bool TargetLoweringBase::allowsMemoryAccessForAlignment(
Fast);
}
-bool TargetLoweringBase::allowsMemoryAccess(
- LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
- unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
- return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
- Flags, Fast);
+bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
+ const DataLayout &DL, EVT VT,
+ unsigned AddrSpace, Align Alignment,
+ MachineMemOperand::Flags Flags,
+ bool *Fast) const {
+ return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace,
+ Alignment.value(), Flags, Fast);
}
bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
const DataLayout &DL, EVT VT,
const MachineMemOperand &MMO,
bool *Fast) const {
- return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
- MMO.getAlign().value(), MMO.getFlags(), Fast);
+ return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
+ MMO.getFlags(), Fast);
}
BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 333561f0b2f0..04bc40a29704 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3394,12 +3394,12 @@ EVT HexagonTargetLowering::getOptimalMemOpType(
return MVT::Other;
}
-bool HexagonTargetLowering::allowsMemoryAccess(LLVMContext &Context,
- const DataLayout &DL, EVT VT, unsigned AddrSpace, unsigned Alignment,
- MachineMemOperand::Flags Flags, bool *Fast) const {
+bool HexagonTargetLowering::allowsMemoryAccess(
+ LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
+ Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
MVT SVT = VT.getSimpleVT();
if (Subtarget.isHVXVectorType(SVT, true))
- return allowsHvxMemoryAccess(SVT, Alignment, Flags, Fast);
+ return allowsHvxMemoryAccess(SVT, Flags, Fast);
return TargetLoweringBase::allowsMemoryAccess(
Context, DL, VT, AddrSpace, Alignment, Flags, Fast);
}
@@ -3409,7 +3409,7 @@ bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
MachineMemOperand::Flags Flags, bool *Fast) const {
MVT SVT = VT.getSimpleVT();
if (Subtarget.isHVXVectorType(SVT, true))
- return allowsHvxMisalignedMemoryAccesses(SVT, Alignment, Flags, Fast);
+ return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);
if (Fast)
*Fast = false;
return false;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 1c123c06bf32..7d6e6b6185c8 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -306,8 +306,9 @@ namespace HexagonISD {
const AttributeList &FuncAttributes) const override;
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
- unsigned AddrSpace, unsigned Alignment, MachineMemOperand::Flags Flags,
- bool *Fast) const override;
+ unsigned AddrSpace, Align Alignment,
+ MachineMemOperand::Flags Flags,
+ bool *Fast) const override;
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast)
@@ -408,10 +409,11 @@ namespace HexagonISD {
VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
- bool allowsHvxMemoryAccess(MVT VecTy, unsigned Alignment,
- MachineMemOperand::Flags Flags, bool *Fast) const;
- bool allowsHvxMisalignedMemoryAccesses(MVT VecTy, unsigned Align,
- MachineMemOperand::Flags Flags, bool *Fast) const;
+ bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags,
+ bool *Fast) const;
+ bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
+ MachineMemOperand::Flags Flags,
+ bool *Fast) const;
bool isHvxSingleTy(MVT Ty) const;
bool isHvxPairTy(MVT Ty) const;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index bf9ddef12882..7cda915fffe9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -299,9 +299,8 @@ HexagonTargetLowering::isHvxBoolTy(MVT Ty) const {
Ty.getVectorElementType() == MVT::i1;
}
-bool
-HexagonTargetLowering::allowsHvxMemoryAccess(MVT VecTy, unsigned Alignment,
- MachineMemOperand::Flags Flags, bool *Fast) const {
+bool HexagonTargetLowering::allowsHvxMemoryAccess(
+ MVT VecTy, MachineMemOperand::Flags Flags, bool *Fast) const {
// Bool vectors are excluded by default, but make it explicit to
// emphasize that bool vectors cannot be loaded or stored.
// Also, disallow double vector stores (to prevent unnecessary
@@ -315,9 +314,8 @@ HexagonTargetLowering::allowsHvxMemoryAccess(MVT VecTy, unsigned Alignment,
return true;
}
-bool
-HexagonTargetLowering::allowsHvxMisalignedMemoryAccesses(MVT VecTy,
- unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const {
+bool HexagonTargetLowering::allowsHvxMisalignedMemoryAccesses(
+ MVT VecTy, MachineMemOperand::Flags Flags, bool *Fast) const {
if (!Subtarget.isHVXVectorType(VecTy))
return false;
// XXX Should this be false? vmemu are a bit slower than vmem.
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